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Virtex UltraScale+ Box

Xilinx Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit (Passive)

  • Part Number: DK-U1-VCU1525-P-G
  • Lead Time: Contact Sales
  • Device Support:

Product Description

Ideal for data center application developers wanting to leverage the advanced capabilities of Virtex® UltraScale+™ FPGAs. This PCIe® development board is accessible in the cloud and on-premise with the frameworks, libraries, drivers and development tools to support easy application programming with OpenCL™, C, C++ and RTL through the Xilinx SDAccel™ Development Environment.

Actively Cooled Version


Key Features & Benefits

  • Specialized reprogrammable hardware for computationally intensive applications, specifically targeting the fast-growing markets for live video transcoding, data analytics, genomics, and machine learning
  • Dual slot PCIe 3/4-length full height form-factor compliant
  • Delivers 10-100x performance acceleration over server CPUs with a board designed to support up to 225W
  • SDAccel platform reference design for custom board support
  • Supported with SDAccel Development Environment for OpenCL, C, C++ and RTL
  • VU9P Virtex UltraScale+ FPGA
  • 21 TOPs (8-bit integer precision)
  • 346Mb on chip memory
  • 64GB on board DDR4 DIMM memory

Board Features

Featuring the VCU1525 Board

vcu1525_callout

Memory

  • 4 - 16GB DDR4 DIMMs

Power & Thermal

  • Passive Cooling (Airflow across heat sink must be provided by user)
  • 225W Max Dynamic Power Sourcing
  • Up to 75W max from PCIe Edge Connector
  • Additional 150 W max supplied from PCIe Aux Power Connector

Configuration

  • FPGA Configuration via JTAG thru Micro USB Port
  • QSPI Configuration flash memory

Communication & Networking

  • Two QSFP28 100G Interfaces
  • PCIe Gen3 x 16 or Gen4 x8 via Edge Connector

Featured Xilinx Devices

Featuring the XCVU9P-L2FSGD2104E FPGA

System Logic Cells (K) 2,586
DSP Slices 6,840
Memory (Mb) 345.9
GTY 32.75Gb/s Transceivers 76
I/O 676
virtex-ultrascale-plus-bk-chip

What's Inside

VCU1525 board featuring the XCVU9P-L2FSGD2104E

Vivado® Design Suite: Design Edition Voucher Code

Node locked & Device-locked to the XCVU9P FPGA, with 1 year of updates

USB Micro Cable

Step 1: Board Revision
Step 2: Tools Version
Step 3:

Design Tools

Name Description License Type
Vivado Design Suite Design Edition The Xilinx Vivado® Design Suite is a revolutionary IP and System Centric design environment built from the ground up to accelerate the design for all programmable devices. Node locked and device-locked to the XCVU9P FPGA, with one year of updates.

Supports partial reconfiguration
SDAccel Development Environment SDAccel is a development environment for OpenCL applications targeting PCIe®-based Xilinx FPGA accelerator cards. This environment enables concurrent programming of the system processor and the FPGA logic without the need for RTL design experience. Node locked and device-locked to the XCVU9P FPGA, with one year of updates.
Partial Reconfiguration Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption. Xilinx Partial Reconfiguration technology allows designers to change functionality of the accelerator board on the fly, eliminating the need to fully reconfigure and re-establish PCIe links while reloading. Node locked and device-locked to the XCVU9P FPGA, with one year of updates.

Intellectual Property

Name Description License Type
DDR4 SDRAM Controller DDR4 SDRAM controller is a free IP core in the Vivado IP Catalog. No-Charge IP
DMA for PCI Express (PCIe) Subsystem The Xilinx® LogiCORE™ DMA for PCI Express (PCIe) implements a high performance, configurable Scatter Gather DMA for use with the PCI Express 3.x integrated block.  The IP provides an optional AXI4 or AXI4-Stream user interface. No-charge IP
Xilinx SmartConnect Technology The Xilinx SmartConnect Technology enables unprecedented levels of performance for the UltraScale+™ device portfolio, by solving the system interconnect bottlenecks on high density, multi-million system logic cell designs. No-charge IP
SDAccel Platform Reference Design for Custom Board Support SDAccel projects are compiled against a target platform. The SDAccel Platform Reference Design is the combination of board and hardware/software infrastructure components on which the kernels of an OpenCL application are executed.  This reference design is intended to be used as a starting point to help platform developers add SDAccel support for their custom PCIe boards. No-charge IP
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