UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

UltraScale+ Device Integrated Block for PCI Express (PCIe)

Product Description

The Xilinx® UltraScale+ FPGA Integrated Block for PCI Express® solution IP core is a high-bandwidth, scalable, and reliable serial interconnect building block solution for use with UltraScale+™ devices. The Integrated Block for PCI Express (PCIe) solution supports 1-lane, 2-lane, 4-lane, 8-lane, and 16-lane Endpoint configurations, including Gen1 (2.5 GT/s), Gen2 (5.0 GT/s) and Gen3 (8 GT/s) speeds. This solution supports the AXI4-Stream.

Key Features & Benefits

  • Designed to PCI Express Base Specification 3.1
  • PCI Express Endpoint, Legacy Endpoint or Root Port Port Modes
  • x1, x2, x4, x8 or x16 link widths
  • Gen1, Gen2 and Gen3 link speeds
  • PHY only mode available
  • AXI4 Streaming Interface to customer logic
    • Configurable 64-bit/128-bit/256-bit/512-bit data path widths
    • Four Independent Initiator/Target, Request/Completion Streams
  • Parity protection on internal logic data paths and data interfaces
  • Advanced Error Reporting (AER) and End-to-End CRC (ECRC)

Featured Documents

Tools and Device Support

Device Family Support:

Design Tools Support:

Related Products

xilinx-131x43
  • Bundled With: Vivado Design Suite
  • License: Xilinx End User License Agreement

Featured Documents

Page Bookmarked