High Level Design Features
Here's a quick overview of Vivado™ ML features for Accelerating High-Level Design. Click the other tabs for complete feature details.
The advanced algorithms used today in AI, wireless, medical, defense, and consumer applications are more sophisticated than ever before. The Vitis™ High-Level Synthesis tool, included as a no-cost upgrade in all Vivado™ Editions, accelerates IP creation by enabling C++ specifications to be directly targeted into AMD programmable devices without the need for manually creating equivalent RTL designs. The Vitis HLS tool supports both the Vitis and Vivado design environments, and enables software and hardware designers alike to accelerate kernel or IP creation through:
The following built-in libraries are included with the Vitis HLS tool:
Arbitrary Precision Data Types
Integer and fixed-point (ap_int.h) types
Models for streaming data structures—designed to obtain best performance and area (hls_stream.h)
Vectorized types and operations (hls_vector.h) including for arbitrary precision types
Extensive support for the synthesis of standard C (math.h) and C++ (cmath.h) math libraries.
Support includes floating-point and fixed-point functions: abs, atan, atanf, atan2, atan2, ceil, ceilf, copysign, copysignf, cos, cosf, coshf, expf, fabs, fabsf, floorf, fmax, fmin, logf, fpclassify, isfinite, isinf, isnan, isnormal, log, log10, modf, modff, recip, recipf, round, rsqrt, rsqrtf, 1/sqrt, signbit, sin, sincos, sincosf, sinf, sinhf, sqrt, tan, tanf, trunc
The Vitis HLS tool also supports the Vitis performance-optimized libraries available on GitHub with out-of-the-box acceleration and minimal-to-zero code changes to your existing applications. These common Vitis accelerated-libraries include advanced math, statistics, linear algebra, and DSP to offer core functionalities for a wide range of applications. These libraries offer acceleration for workloads such as vision and image processing with OpenCV functions, quantitative finance, database, data analytics, data compression, and more.
For more information, please visit the Vitis HLS site.
The Vivado™ ML Edition shatters the RTL design productivity plateau by providing the industry’s first plug-and-play IP integration design environment, with its IP Integrator feature.
Vivado IP Integrator provides a graphical and Tcl-based, correct-by-construction design development flow. It provides a device and platform aware, interactive environment that supports intelligent auto-connection of key IP interfaces, one-click IP subsystem generation, real-time DRCs, and interface change propagation, combined with a powerful debug capability.
Designers work at the “interface” and not “signal” level of abstraction when making connections between IP, greatly increasing productivity. Often times this is using industry standard AXI4 interfaces, but dozens of other interfaces are also supported by IP integrator.
Working at the interface level, design teams can rapidly assemble complex systems that leverages IP created with Vitis HLS, Model Composer, AMD SmartCore™ and LogiCORE™ IP, Alliance Member IP as well as your own IP. By leveraging the combination of Vivado IPI and HLS customers are saving up to 15X in development costs versus an RTL approach.
As the leading provider of Electronic System Level Design tools for programmable solutions, Vivado provides Vitis™ High-Level Synthesis for C, C++ and SystemC, and you can buy an add-on Vitis model composer for DSP. These solutions enable high-level IP specifications to be directly synthesized into VHDL and Verilog, accelerating IP verification over 100X and RTL creation by up to 4X. The highly integrated tools can be used individually or in combination with the result being reusable IP for use in the Vivado ML Suite.
Dynamic Function eXchange is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption. AMD DFX technology allows designers to change functionality on the fly, eliminating the need to fully reconfigure and re-establish links, dramatically enhancing the flexibility that FPGAs and SoCs offer; it is a key capability for platform-based design flows, most notably for Alveo accelerator cards. The use of Dynamic Function eXchange can allow designers to move to fewer or smaller devices, reduce power, and improve system upgradability. Make more efficient use of the silicon by only loading in functionality that is needed at any point in time.
The Vivado™ ML Design Suite software tools unlock the capability to reconfigure a portion of a AMD FPGA or SoC while the rest of the device remains operational. The current solution leverages the impressive implementation capabilities of the Vivado ML Design Suite, reducing the overhead necessary to create reconfigurable designs. Users can implement designs using the Tcl-based non-project flow or the RTL- or IP-based project flows. IP Integrator (IPI) design support was introduced in version 2021.1 through the use of Block Design Containers. RTL and IP project modes are supported within the Vivado IDE, with many underlying flow details automatically managed. Entry points to the design flow include high level languages processed via Vitis and HLS. Advanced flow features such as Nested DFX, which enables users to subdivide a dynamic region into lower-order dynamic regions, and Abstract Shell, which streamlines the implementation tool flow, greatly improving runtime, are available in non-project mode.
Four pieces of intellectual property are available to help designers complete DFX designs more quickly and easily. The Dynamic Function eXchange Controller is a hardware-based configuration controller that can help manage all aspects of reconfiguration events, from triggering and arbitration to bitstream delivery and error handling. The Dynamic Function eXchange Decoupler can be used with the DFX Controller or with any customer controller to safely isolate the dynamic region as it is being reconfigured. The Dynamic Function eXchange AXI Shutdown Manager helps users cease activity on AXI interfaces so Reconfigurable Partitions can be safely reconfigured. The Dynamic Function eXchange Bitstream Monitor allows users to debug and monitor partial bitstreams, ensuring version and target compatibility.
Most 7 series and Zynq™ 7000 devices support Dynamic Function eXchange, with the only exceptions being the smallest devices within these families; some Artix 7 and all Spartan 7 are not supported. UltraScale™ support is complete, with all devices supported through bitstream generation in the current Vivado Design Suite version. UltraScale+™ device support covers all devices in production. Versal support was added with production status in Vivado 2021.1. See the DFX Reconfiguration User Guide (UG909), Appendix A, for the most up-to-date list.
UltraScale represented a new breakthrough in Dynamic Function eXchange technology, enabling reconfiguration of nearly all FPGA resource types, including I/O, Gigabit Transceivers, and clocking networks. UltraScale+ improved upon this capable family by streamlining bitstream delivery and expanding reconfiguration modes. Most recently, Versal support is a tremendous step forward in efficiency with software-based reconfiguration management, a reconfigurable network-on-chip, shared memory access, and floorplan granularity efficiencies.
Professors and researchers associated with universities may receive licenses for versions of Vivado software through the AMD University Program. All Vivado editions include Dynamic Function eXchange but older versions (prior to 2019) have explicit DFX license requirements. Learn more about access requirements and procedures for obtaining licenses by sending an email to email@example.com.
Abstract Shell is a new technology that enables fast compile for complex and large designs. It allows users to define reconfigurable modules within a design to be compiled independently. Users can select portions of the design to be modified and recompiled without having to recompile the entire design.
Abstract Shell enables an average compile time reduction of 5x and up to 17x compared to a traditional compilation. This features also allows users to define multiple modules within the design that can be compiled in parallel.
Vitis™ Model Composer is a Model-Based Design tool that enables rapid design exploration within the MathWorks MATLAB® and Simulink® environment and accelerates the path to production on AMD devices through automatic code generation. You can design your algorithms and iterate through them using high-level performance-optimized blocks and validate functional correctness through system-level simulations. Vitis Model Composer transforms your design to production-quality implementation through automatic optimizations. The tool provides a library of more than 200 HDL, HLS, and AI Engine blocks for the design and implementation of algorithms on AMD devices. It also enables importing custom HDL, HLS, and AI Engine code as blocks into the tool. Vitis Model Composer includes all the functionality of AMD System Generator for DSP which is no longer shipped as a standalone tool since 2020.2.
In Vitis Model Composer you can:
Vitis Model composer can be purchased as an add-on license to any Vivado ML Edition.
For more information on how to download and buy please visit the Vitis Model Composer page.
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