PlanAhead™ streamlines design iterations between synthesis and implementation. With PlanAhead, you can easily view implementation and timing results to analyze critical logic, and make targeted decisions to improve design performance with floorplanning, constraint modification, and multiple implementation tool options. It helps you make tradeoffs between RTL Coding and Synthesis and Implementation, with extensive design exploration and analysis features.
With convenient access through the integration with the ISE Project Navigator, PlanAhead extends the methodology of the logic design flow to help users get the most out of their design through floorplanning, multiple implementation runs, hierarchy exploration, quick timing analysis, and block based implementation.
PlanAhead also provides easy and convenient method of placing the ChipScope Pro debug cores to make simplify the process of on-chip verification.
Simplified Pin Planning
PlanAhead provides features to help users simplify the complexities of pin assignments with an environment for fully automatic or semi-automated assignment of I/O ports to physical Package Pins.
Implementation Management
PlanAhead includes an implementation exploration tool. By managing multiple implementation runs, PlanAhead allows the user to execute multiple implementation runs based on strategies they’ve defined or predefined strategies shipped as factory defaults. In a Linux environment, PlanAhead provides the ability to run the implementation on remote hosts.
Block-Based, Incremental Design
PlanAhead supports a hierarchical, block-based, modular and incremental design methodologies, enabling designers to change only part of the design, leaving placement of the rest intact, thereby shortening design iterations. It helps you consistently maintain the required performance, even while making frequent changes.
Signal Integrity
PlanAhead includes functionality to check limits for Weighted Average SSO (WASSO) analysis. This allows designers to more easily limit the amount of ground bounce present immediately at the output of the FPGA and prevent corruption of the operation of other devices driven by the FPGA.
TimeAhead
TimeAhead is a flexible timing analyzer integrated into PlanAhead. It allows you to estimate route delays before running place and route. Using the PlanAhead block-based approach, the accuracy of timing estimates will improve as blocks in the design are implemented through place and route.