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MIPI CSI Controller Subsystems

Product Description

The Xilinx MIPI CSI2 Receiver Subsystem and MIPI CSI 2 Transmitter Subsystems implement the Mobile Industry Processor Interface (MIPI) based Camera Serial Interface (CSI-2) according to version 1.1 on Xilinx's UltraScale+™ devices and allows users to capture raw images from MIPI CSI2 camera sensors or transmit to MIPI based Image sensor processors. The CSI2 Receiver and Transmitter can be implemented in Xilinx UltraScale+ FPGAs without requiring external D-PHY bridges. Xilinx 7-series devices require external D-PHY bridges or passive components to implement D-PHY layer. The subsystems allow fast selection of the top level parameters and automate most of the lower level parameterization. The AXI4 streaming interfaces make it easy for other AXI4 based subsystems to seamlessly plug into the CSI controllers.

Key Features & Benefits

The MIPI CSI2 Receiver and Transmitter subsystems are designed to be compliant with the MIPI CSI-2 version 1.1 specification standard and includes the following features

  • Support for 1 to 4 PPI Lanes
  • Line rates ranging from 80 to 1500 Mb/s depending on the device family
  • Multiple data type support (RAW,RGG,YUV)
  • AXI IIC support for CCI interface
  • Filtering based on Virtual Channel ID (VC)
  • Single, Dual, Quad pixel support at output
  • Interface compliant to UG934 format with support for 4K resolution imagers and processors
  • Small resource count
xilinx-131x43
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  • Part Number:
    EF-DI-MIPI-CSI-RX-SITE
    EF-DI-MIPI-CSI2-TX-SITE
  • License: Core License Agreement

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