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MIPI DSI TX Controller Subsystem

Product Description

The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem implements the Mobile Industry Processor Interface (MIPI) based display interface.  The Display Serial Interface Specification defines protocols between a host processor and peripheral devices using a D-PHY physical interface. The DSI specification builds on existing specifications by adopting pixel formats and command set defined in MIPI Alliance specifications for Display Pixel Interface 2 (DPI-2) and Display Command Set (DCS) 

Key Features & Benefits

The MIPI DSI Transmitter subsystem is designed to be compliant with the MIPI DSI version 1.3 specification standard and includes the following features

  • Compliant with the MIPI DSI  Interface Specification, rev. 1.3
  • Standard PPI interface towards D-PHY
  • 1-4 Lane Support
  • Maximum Data Rate – 1.5 Gigabits per second
  • Supports all mandatory data types
  • Virtual channel (1 to 4)Programmable EoTp generation support
  • Low Power (LP) and Ultra Low Power(ULP) mode generation
  • Multilane interoperability
  • ECC generation for packet header
  • CRC generation for data bytes(Can be Optional)
  • Pixel byte conversion based on data format
  • AXI4-Lite interface to access core registers
  • Compliant with UG934 for input video stream
xilinx-131x43
Order Evaluate
  • Part Number:
    EF-DI-MIPI-DSI-TX-SITE
  • License: Core License Agreement

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