Versal Adaptive SoC Integrated Block for PCI Express
- Bundled With:
- Vivado Design Suite
- License: End User License Agreement
Product Description
The Versal™ adaptive SoC Integrated Block for PCI Express® is a building block IP for high-bandwidth, scalable, and reliable serial interconnect based on the PCI Express specification. Designs that configure an available programmable logic integrated block for PCI Express (PL PCIE) can realize a specific implementation of the PCI Express Base Revision 4.0 (PL PCIE4) or the PCI Express Base Revision 5.0 (PL PCIE5).
Key Features and Benefits
- Versal devices with PL PCIE5 support:
- Maximum link width based on available GTYP in the selected device/package.
- Gen1 (2.5 GT/s/lane), Gen2 (5.0 GT/s/lane), Gen3 (8.0 GT/s/lane) rates at up to x16 link widths
- Gen4 (16.0 GT/s/lane) rate at up to x8 link widths
- Gen5 (32.0 GT/s/lane) rate at up to x4 link widths
- Versal devices with PL PCIE4 support:
- Maximum link width based on available GTY in the selected device/package
- Gen1 (2.5 GT/s/lane), Gen2 (5.0 GT/s/lane), Gen3 (8.0 GT/s/lane) rates at up to x16 link widths
- Gen4 (16.0 GT/s/lane) rate at up to x8 link widths
- Endpoint, Root Port, Switch Port Upstream, Switch Port Downstream, and Legacy Endpoint modes
- AXI4-Stream transaction-layer interfaces to programmable logic (RQ/RC/CQ/CC)
- Advanced error reporting (AER) and end-to-end CRC (ECRC)
- One virtual channel, eight traffic classes
- Single-root I/O virtualization (SR-IOV)
- MSI-X, MSI, and INTx interrupt support
Support
Design Tools:
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