Product Description

ZipAccel-D is a custom hardware implementation of a lossless data decompression engine that complies with the Inflate/Deflate, GZIP/GUNZIP, and ZLIB compression standards.

The core features fast processing, with low latency and high throughput. On average the core outputs two bytes of decompressed data per clock cycle, providing over 2Gbps in most AMD FPGAs. Designers can scale the throughput further by instantiating the core multiple times to achieve throughput rates exceeding 100Gbps. The latency for blocks coded with Static Huffman is in the order of few tens of clock cycles, and blocks coded with Dynamic Huffman get processed in less than 1500 cycles.

The decompression core has been designed for ease of use and integration. It operates on a standalone basis, off-loading the host CPU from the demanding task of data decompression. The core receives compressed input files and outputs decompressed files. No preprocessing of the compressed files is required, as the core parses the file headers, checks the input files for errors, and outputs the decompressed data payload. Featuring extensive error tracking and reporting errors, the core enables smooth system operation and error recovery, even in the presence of errors in the compressed input files. Furthermore, internal memories can optionally support Error Correction Codes (ECC) to simplify achievement of Enterprise Class reliability requirements.

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