MicroBlaze Soft Processor Core

The MicroBlaze™ core is a 32-bit RISC Harvard architecture soft processor core with a rich instruction set optimized for embedded applications. With the MicroBlaze soft processor solution, you have complete flexibility to select the combination of peripherals, memory and interface features that will give you the exact system you need at the lowest cost on a single FPGA. Being reconfigurable, it will help you get your products to market faster—and keep them in the market longer.

Choose From Two Performance Levels

MicroBlaze has over 70 configuration options, enabling everything from a very small footprint microcontroller, all the way up to high performance embedded computer running Linux. At the heart of this flexibility are the two versions of MicroBlaze, the 3-pipeline stage area-optimized MicroBlaze and the 5-pipeline stage performance-optimized MicroBlaze. Use the 3-pipeline stage version if you want as small a footprint as possible or use the 5-stage pipeline for the highest performance.

MicroBlaze Processor v7.2 Performance Levels
Architecture	Performance	Maximum Clock Frequency	Maximum Dhrystone 2.1 Performance
5-Stage Pipeline	1.19 DMIPs/MHz	235 MHx in Virtex®-5 FXT	280 DMIPS
3-Stage Pipeline	0.95 DMIPs/MHz	106 MHz in Spartan®-3A DSP	100 DMIPS
* Both 3-stage pipeline and 5-stage pipeline versions of MicroBlaze run in all Virtex and Spartan devices supported in EDK.

MicroBlaze Floating Point Unit

The MicroBlaze soft processor has an optional integrated Floating-Point Unit (FPU). Floating point math is often a requirement for industrial control, automotive and scientific applications. IEEE-754 compatible FPU connects directly to the MicroBlaze instruction execution pipeline, ensuring high performance, low latency and a compact design. Because the MicroBlaze FPU is a configurable part of the MicroBlaze core, it takes no extra space in the FPGA if it is not needed.

The MicroBlaze FPU is fully supported by the Embedded Development Kit (EDK). The GNU compiler will automatically take advantage of the FPU by moving the floating point execution from software libraries to hardware. No changes are required to your source code. The MicroBlaze soft processor core with the FPU is licensed as part of the EDK.

Floating point acceleration is often demanded by applications targeting industries such as industrial control, automotive, scientific, military and aerospace.

MicroBlaze Processor v7.2 FPU: Single Precision
FPGA	Size	Maximum Clock Frequency	Peak Floating Point Throughput
Virtex-5	<1650 LUTs (850 FPU + 800 MB)	200 MHz	50 MFLOPS

FPU Performance

The following table shows the maximum floating-point performance that MicroBlaze can achieve with an FPU and its corresponding area. The targeted system includes a GPIO and the FPU block. Execution is done from on-chip memory.

Comparative speeds for floating point performance

The speed increase over software floating point execution depends on the application. These are relative numbers with and without the FPU.

Network Performance

It's a new day and even the simplest embedded systems often require Ethernet connectivity. Xilinx FPGAs provide a variety of Ethernet IP that can be easily used with MicroBlaze with the following results.

125 MHz MicroBlaze / 125 MHz MPMC / 125 MHz PLB46 System on ML505 Board
Packet Size (bytes)	10 Mbit Link (Mbps)	100 Mbit Link (Mbps)	1000 Mbit Link (Mbps)
64	7.619	76.19	761.9
128	8.611	86.11	861.1
512	9.624	96.24	962.4
1518	9.870	98.70	987.0
9000	9.978	99.78	997.8
Results from XAPP 1041: Reference System: XPS LL Tri-Mode Ethernet MAC Embedded System for MicroBlaze and PowerPC Processors

Maximum Configurability

A rich assortment of IP cores for MicroBlaze gives you an unprecedented amount of flexibility in building your embedded system. But MicroBlaze itself is highly configurable, giving you yet another degree of flexibility in designing your platform. With over 70 configurable features you can select exactly the system you need at whatever performance or density target you have.

Configuration Features

Memory Management Unit (MMU)

Full MMU with Virtual Memory supported by Linux 2.6
MPU mode for region protection for secure RTOS applications

Floating Point Unit

IEEE 754 compatible
Single precision

Hardware Exception Support

Unaligned access
Illegal instruction
Data bus error
Instruction bus error
Divide-by-zero

Instruction and Data Caches

Uses on-chip block RAM primitives
Configurable size 2kB - 64kB
Configurable micro-cache (using distributed RAM) size 64B – 1024B
Direct mapped write-through operation

Barrel Shifter

1 cycle operation

Hardware Integer Divide

32 cycle operation

Hardware Multiply

1 cycle operation
MUL64 operation

Instruction Set Extensions

Pattern Compare Instructions
Machine Status Register Set and Clear
Atomic Access

Multiple Buses Accommodate Different Performance Needs

Local Memory Bus (LMB) for fast local access memory
Xilinx Cache Link point to point interface for direct connect between cache and external memory
Processor Local Bus (PLB46) for connecting multiple peripherals directly to MicroBlaze
Up to 16 Fast Simplex Link (FSL) Co-processor Links for hardware acceleration

Interrupt Signaling

Edge or level
Active high or low

Debug Logic

JTAG control via a debug support core
Up to 8 hardware break points
Integrated Trace port

Processor Version Register

The Complete Solution

MicroBlaze is just part of the complete Xilinx embedded solution. There is also Processor Central to learn more about Platform Studio, the design environment for building your embedded system; the Software Development Kit; all of the IP that comes with the Embedded Development Kit; and the ever-expanding 3rd Party Ecosystem that continues to grow around MicroBlaze.