USB3 Vision Camera IP Core
- Part Number: U3V DEVICE V1.1.0
- Vendor: Sensor to Image GmbH
- Partner Tier: Select Certified
Product Description
USB3 Vision is a standard communication protocol for vision applications based on the widely used USB 3.0 interface. As the protocol is standard and supports GenICam, it allows easy interfacing between cameras and PCs. Sensor to Image offers a set of IP cores and a development framework to build FPGA-based products using the USB3 Vision interface.
Key Features and Benefits
- Control Channel handled by embedded CPU, typically a Cypress FX3
- Full functional reference designs available
- AMD AXI4 memory controller supported
- Hardware implementation of Stream Channel to reach maximum throughput
- Implementation of the AIA USB3 Vision Protocol
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| ARTIX-7 Family | XC7A200T | -2 | Vivado 2019.1 | Y | 5680 | 12674 | 13 | 0 | 2 | 0 | 100 |
| Zynq-7000 Family | XC7Z015 | -2 | Vivado 2019.1 | Y | 3492 | 6985 | 8 | 0 | 0 | 0 | 100 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | 1.1.0 |
| Date Current Revision was Released | Feb 19, 2021 |
| Release Date of First Version | Oct 17, 2013 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 25 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Source Code, Netlist |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | Y |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Artix-7 |
| Software Drivers Provided? | Y |
| Driver OS Support | PC: Windows, LINUX |
Implementation
| Code Optimized for Xilinx? | N |
| Synthesis Software Tools Supported/Version | Vivado Synthesis |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4 |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Directed Testing |
| Assertions | Y |
| Coverage Metrics Collected | Assertion, Code, Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Mentor ModelSIM |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | AC701, KC705, MVDK |
| Industry Standard Compliance Testing Passed | Y |
| Specific Compliance Test | AIA USB3 Vision Validation |
| Test Date | Feb 16, 2021 |
| Are Test Results Available? | Y |