Product Description
The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (2**64 – 1) bits. Developed for easy reuse, the SHA-256 is available optimized for several technologies with competitive utilization and performance characteristics. Support for the AMBA bus interfaces is available as an option.
Key Features and Benefits
- Maximum message length up to (2**59 – 1) bits
- Throughput: 7.9 Mbits/MHz
- Deliverables include test benches, C model and test vector generator
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Kintex-UP Family | XCKU11P | -1 | Vivado 2020.1 | 0 | 1008 | 0 | 0 | 0 | 0 | 400 | |
| KINTEX-U Family | XCKU085 | -1 | Vivado 2020.1 | 0 | 1050 | 0 | 0 | 0 | 0 | 300 | |
| VIRTEX-7X Family | XC7VX330T | -3 | Vivado 2015.4 | 351 | 1120 | 0 | 0 | 0 | 0 | 150 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | 1.3 |
| Date Current Revision was Released | Oct 02, 2019 |
| Release Date of First Version | Feb 24, 2005 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 7 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Netlist, Source Code |
| Source Code Format(s) | VHDL, |
| High-Level Model Included? | Y |
| Model Formats | C |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog, VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | UCF |
| Commercial Evaluation Board Available? | N |
| FPGA Used on Board | N/A |
| Software Drivers Provided? | N |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis; Mentor Precision; Vivado Synthesis |
| Static Timing Analysis Performed? | Y |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | N |
| Simulators Supported | Synopsys VCS; Other; Cadence NC-Sim; Mentor ModelSIM; Mentor Questa |
Hardware Validation
| Validated on FPGA | N |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |