ONFI 3.1 Controller
- Price: $35,000.00
- Part Number: ACS-DIP-ONFI31
- Vendor: Arasan Chip Systems, Inc.
- Partner Tier: Elite
Product Description
The IP core supports Open Nand Flash Interface Working Group (ONFI) 3.1 standard and backward compatible to earlier versions. Tools used Vivado 2022.1 Arasan's IP is also available to license for ASIC applications. Arasan offers a licensing scheme to go from FPGA to ASIC at reduced license fees.
Key Features and Benefits
- Supports all mandatory commands and selected optional commands
- Supports speed ranging from 40MB/s to 400MB/s to allow applications to balance performance and power
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-UP Family | XCVU9P | -2 | Vivado ML 2022.1 | 18902 | 106936 | 0 | 0 | 0 | 0 | 200 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | 3p13 |
| Date Current Revision was Released | Aug 29, 2015 |
| Release Date of First Version | Mar 29, 2013 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 10 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Source Code |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | Y |
| Model Formats | Other |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog |
| Code Coverage Report Provided? | Y |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | SDF |
| Commercial Evaluation Board Available? | N |
| FPGA Used on Board | N/A |
| Software Drivers Provided? | N |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | UltraFast Design Methodology |
| Custom FPGA Optimization Techniques | Vivado |
| Synthesis Software Tools Supported/Version | Xilinx XST |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Lite |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Directed Testing |
| Assertions | Y |
| Coverage Metrics Collected | Code |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Cadence NC-Sim |
Hardware Validation
| Validated on FPGA | N |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |