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System Level Design and Verification in Versal ACAP

This session will introduce the Versal ACAP system-level design methodology. In this session you will learn the basics of the new Network on Chip technology and corresponding design methodology of how to design a hardware platform for Versal with the NoC and DDR. You will learn how to go from paper mapping to the new IP Integrator tools and how to simulate the design with traffic generators. The design will then be taken through the implementation tools to generate the programmable image.