UPGRADE YOUR BROWSER
We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Learn More about Xilinx’s Accelerated Cloud Service Partners
Download the Latest Xilinx Tools
Documentation Navigator Download Today
Community Forums Get Support
Connect - Learn - Share Join Us at Xilinx Developer Forum
Forgot your username or password?
New to Xilinx? Create your account
By signing in, you agree to the Xilinx Terms of Use and Privacy Policy.
Create basic Verilog module description by properly declaring ports and building hierarchy.