We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Generating Vivado HLS Pcore for use in Xilinx Platform Studio

Learn how to generate a pcore IP block using Vivado HLS for use in Xilinx Platform Studio. This video explains everything you need to known about the Export RTL feature, including device & license support, the other available export formats and how to evaluate the Vivado HLS design by launching RTL synthesis from within Vivado HLS. This video ends with a summary of how the Vivado HLS IP can be imported into Xilinx Platform Studio as a pcore.

Page Bookmarked