112G PAM4 transceivers and their performance

This demonstration shows basic operation of the test chip transceiver with a GUI showing the line rate, equalization values, and BER showing performance orders of magnitude better than required by the applicable specification. With an advanced ADC-based receiver and DFE/FFE implemented in DSP, this test chip and the GTM transceiver can support protocols ranging from super-low loss OIF-CEI-112G-XSR to high-loss cabled interconnects like 100GBase-CR4.