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Through a series of tutorials and paper presentations, Xilinx experts shared their insights for overcoming system-design challenges in various  technical areas, including High-Speed Serial Design, Signal and Power Integrity, and Memory Interfacing.

Papers and Presentations

Design of Flyover QSFP (FQSFP) Design for 56+Gb/s (Paper) (Presentation)

End-to-End System-Level Analyses for PCIe-4.0 (Paper) (Presentation)

Characterization of DDR4 Receiver Impact on Post-Equalization Eye (Paper) (Presentation)

112G Serial Transmission over Copper PAM4 vs PAM8 Signaling (Paper) (Presentation)

IBIS-AMI Modeling and Simulation of using Duobinary Signaling (Paper) (Presentation)

IBIS-AMI Modeling of Asynchronous High Speed Link Systems (Paper) (Presentation)

DESIGNING TO EVOLVING LTE ADVANCED PRO ANDPRE-5G REQUIREMENTS (Tutorial)

A Tutorial on PAM4 Signaling for 56G Serial Link Applications (Tutorial)

32G to 56G Link Analysis and Optimization for Pathological Channels (Tutorial)

Papers and Presentations

Investigation of Package Crosstalk and Impact to 28Gbps Transceiver Jitter Margin (Paper)

Novel Methodology of IBIS-AMI Hardware Correlation Using Trend and Distribution Analysis for High-Speed SerDes System (Paper) (Presentation)

Optimal DDR4 System with Data Bus Inversion (Paper) (Presentation)

25G Long Reach Cable Link System Equalization Optimization (Paper) (Presentation)

PAM4 Signaling for 56G Serial Link Applications – A Tutorial (Presentation)

Papers and Presentations

UltraScale DDR4 De-Emphasis and CTLE Feature Optimization with Statistical Engine for BER Specification (Presentation)

IBIS-AMI Model Simulations Over Six EDA Platforms (Presentation)

IBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems (Presentation)

Co-Design for 1TB System Utilizing 28Gbps Transceivers in 20nm Technology (Paper)

A Cure for Intra-Pair Skew in High Speed Differential Signals (Presentation)

UltraScale FPGA DDR4 2400 Mbps System Level Design Optimization and Validation (Presentation)

Papers and Presentations

Relating COM to Familiar S-Parameter Parametric to Assist 25Gb/s System Design (Presentation)

Hands-On Tutorial for Fixture Removal of 28Gb/s Tx Measurements (Zip File)

Touchstone v2.0 SI/PI S-Parameter Models for Simultaneous Switching Noise (Paper) (Presentation)

Distributed Modeling and Characterization of On-Chip/System Level PDN and Jitter Impact (Paper) (Presentation)

Method for Analytically Calculating BER (Bit Error Rate) in Presence of Non-Linearity (Paper) (Presentation)

Model Extraction and Circuit Simulation Approaches for Successful SSO Analysis of Chip-Package-Board Systems (Paper) (Presentation)

High Speed Serial Link Simulation Based on Dynamic Modeling (Paper) (Presentation)

Comprehensive Full-Chip Methodology to Verify Electromigration and Dynamic Voltage Drop on High Performance FPGA Designs
in the 20nm Technology (Paper) (Presentation)

De-Mystifying the 28 Gb/s SERDES Channel - Design to Measurement (Paper) (Presentation)

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