The LogiCORE™ IP JESD204 core is designed to Joint Electron Devices Engineering Council (JEDEC®) JESD204B or JESD204C standard. The JESD204 specifications describe serial data interfaces and the link protocols between data converters and logic devices.
The JESD204B IP core supports line rates of up to 12.5 Gbps characterized to the JESD204B specification and line rates up to 16.1 Gbps not characterized to the JESD204B specification and between 1-32 lane configurations. The IP Core can be configured as JESD204B Transmitter for interfacing to DAC device or JESD204B Receiver for interfacing to ADC device.
The JESD204C IP core implements a JESD204C compatible interface supporting line rates from 1 Gb/s to 32 Gb/s. Each core supports between 1-8 lane configurations and can be combined with other cores to achieve more lanes. The IP Core can be configured as JESD204C Transmitter for interfacing to DAC device using either a 64B66B or 8B10B link layer.
The JESD204 IP cores are delivered as a netlist along with the supporting wrapper files.