The LogiCORE™ IP JESD204 core is designed to Joint Electron Devices Engineering Council (JEDEC®) JESD204B or JESD204C draft standard. The JESD204 specifications describe serial data interfaces and the link protocols between data converters and logic devices.
The JESD204B IP core supports line rates of up to 12.5 Gbps characterized to the JESD204B specification and line rates up to 16.1 Gbps not characterized to the JESD204B specification and between 1-32 lane configurations. The IP Core can be configured as JESD204B Transmitter for interfacing to DAC device or JESD204B Receiver for interfacing to ADC device.
The JESD204C IP core supports line rates of up to 32 Gbps compatible to the JESD204C-100 and JESD204C-300 Draft specifications. Each core supports between 1-8 lane configurations and can be combined with other cores to achieve more lanes. The IP Core can be configured as JESD204C Transmitter for interfacing to DAC device or JESD204C Receiver for interfacing to ADC device.
The JESD204 IP cores are delivered as a netlist along with the supporting wrapper files.
Key Features and Benefits
- Designed to JEDEC JESD204B specification
- Supports scrambling and initial lane alignment
- Supports 1-256 Octets per frame and 1-32 frames per multi-frame
- Supports 1 to 32 lane configurations
- Supports line rates up to 12.5 Gbps certified to the JESD204B spec
- Supports line rates up to 16.3 Gpbs not certified to the JESD204B spec
- Designed to JEDEC JESD204C-100 and JESD204C-300 Draft Standard
- Supports up to eight lanes per core and greater number of lanes using multiple cores
- Supports 64b66b link layer
- Supports CRC and CMD meta data modes
- Supports subclass 0 and 1
- All Versions
- Provides Physical and Data link layer functions
- AXI4-Stream interface for data
- AXI4-Lite for configuration interface