FIR Compiler


Product Description

The Finite Impulse Response (FIR) Filter is one of the most ubiquitous and fundamental building blocks in DSP systems. Although its algorithm is extremely simple, the variants on the implementation specifics can be immense and a large time sink for hardware engineers today, especially in filter-dominated systems like Digital Radios.The FIR Compiler reduces filter implementation time to the push of a button, while also providing users with the ability to make trade-offs between differing hardware architectures of their FIR Filter specification.

Key Features and Benefits

  • Delivers VHDL demonstration testbench with CORE Generator
  • Supports Pipelined Direct-Form based Multiply Accumulate (MAC) FIR and Transposed Direct-Form based MACFIR
  • High-performance finite impulse response (FIR), polyphase decimator, polyphase interpolator, half-band, half-band decimator and half-band interpolator, Hilbert transform, and interpolated filter implementations
  • Advanced interleaved channels to enable implementation of configurable bandwidth feature for advanced systems
  • Multi-column support of DSP48/DSP58 slices for symmetric filter implementations
  • A fixed point bit-accurate C-Model to enable system level analysis of Xilinx FIR Compiler core
  • Multiple implementation architectures: DAFIR, Adder Tree based MACFIR (suitable for Mult18x18 enabled devices) and Adder Chain based MACFIR (suitable for XtremeDSP™ slice enabled devices)
  • Performance reaching up to 680 MHz for Versal devices (-1LP speed grade)
  • Supports 2 -2048 taps
  • Automatic control of hardware folding for the most compact implementation
  • Support for up to 64 channels (Channel = independent stream of voice / data / video, uncorrelated to other such streams that the FPGA is concurrently processing.
  • Interpolation and decimation factors of up to 64 generally and up to 1024 for single channel filters
  • Support for Reloadable Coefficients and up to 16 coefficient sets
  • Automatic Coefficient structure optimizations to reduce area consumed: Symmetry and Halfband
  • Automatic selection of Block vs Distributed Memory for Data and Coefficient storage
  • For use with Vivado® IP Integrator, Vivado IP Catalog™ and Xilinx System Generator for DSP™
  • Support for super sample rate filter configurations
  • For use with Vivado® IP Integrator, Vivado IP Catalog™ and Vitis Model Composer

Resource Utilization



Featured Documents

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Getting Started