The AXI Stream VIP can be used to verify connectivity and basic functionality of AXI Stream masters and AXI Stream slaves with the custom RTL design flow. It also supports Passthrough mode which transparently allows the user to monitor transaction information/throughput or drive active stimulus. The AXI Stream VIP provides example test benches and tests that demonstrate the abilities of AXI4-Stream. These examples can be used as a starting point to create tests for custom RTL design with AXI4-Stream. The examples can be accessed from IP Integrator.
There are no licenses required for use of AXI Stream Verification IP.
Key Features and Benefits
- Supports all protocol data widths and address widths, transfer types and responses
- Full AXI Stream Protocol Checker support
- Integrated ARM Licensed Protocol Assertions
- Transaction level protocol checking (burst type, length, size, lock type, cache type)
- Behavioral SystemVerilog Syntax
- SystemVerilog class-based API
- Configurable simulation messaging
- Delivered in Vivado Design Suite
- SystemVerilog example designs and test benches delivered in IP Integrator
- Supported Simulators: Aldec Riviera-PRO, Cadence Incisive Enterprise Simulator, Vivado Simulator, Mentor Graphics Questa Prime and Synopsys VCS