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Content Addressable Memory (CAM)

Overview

Product Description

Binary CAM (BCAM)

The Binary CAM LogiCORE IP (BCAM) implements an associative array data structure also known as a content-addressable memory. The BCAM stores (key, response) entries with arbitrary key and response bit strings and allows the retrieval of the response based on an exact match of all bits in the search key with all bits in key.

HBM/DDR4 Binary CAM (HBM/DDR BCAM)

The HBM/DDR4 Binary CAM LogiCORE IP (HBM/DDR BCAM) implements an associative array data structure also known as a content-addressable memory using DRAM for storage. The HBM/DDR BCAM stores (key, response) entries with arbitrary key and response bit strings and allows the retrieval of the response based on an exact match of all bits in the search key with all bits in the key. The .solution requires a HBM capable device

Semi-Ternary CAM (STCAM)

The Semi-Ternary CAM LogiCORE IP (STCAM) implements an associative array data structure also known as a content-addressable memory. The STCAM stores (key, mask, priority, response) entries with arbitrary key, mask and response bit strings and allows for the retrieval of the response based on ternary matching of the lookup key. Ternary matching allows multiple entries to match the same lookup key. The entry with lowest priority is selected as the winner. The STCAM supports a limited number of unique masks, that is each mask is shared by multiple entries. This allows for a considerable logic and memory reduction compared to TCAMs. The STCAM is well suited for applications requiring efficient storage of entries using multiple, but a limited number of masks. For example, longest prefix matching of the IP address for IP forwarding tables or OVS mega-flow lookup tables.

Ternary CAM (TCAM)

The Ternary CAM LogiCORE IP (TCAM) implements an associative array data structure also known as a ternary content-addressable memory. The TCAM stores (key, mask, priority, response) entries with arbitrary key, mask, priority and response values and allows the retrieval of the response based on a ternary match of all bits of the masked search key with all bits of the masked key. The key is bit maskable allowing arbitrary bits in the key to be set to ternary state (don't care). Ternary matching allows multiple entries to match and the priority value of the entry determines the winning response.

The CAM solution is based on a combined hardware and software implementation.


Key Features and Benefits

Binary Content Addressable Memory

  • Associative array containing arbitrary (key, response) entries.
  • Exact match key lookup returns hit/miss result and associated response value on hit.
  • High throughput: one lookup per clock cycle up to 600 MHz.
  • Flexible, supports a wide range of key widths, response widths and lookup rates with optimized resource utilization.
  • Supports all key widths up to 992 bits and all response widths up to 1024 bits.
  • Supports both UltraRAM (URAM) and block RAM implementations.
  • Scalable, supports one or multiple BCAM instances, each instance can use all block RAM/UltraRAM (URAM) within an SLR allowing very large BCAMs.
  • High storage efficiency, 95% of the RAM bits are transformed to CAM bits.
  • Supports error correction coding (ECC). Single-bit errors are corrected dynamically during lookups, and permanently with patrol scrubbing.
  • Supports Vivado IP integrator.
  • Supports entry insert, delete, update using standard TCAM like software APIs.
  • Can be inferred from within P4 code using Xilinx® Vitis Networking P4™ tool.

HBM/DDR4 Binary Content Addressable Memory

  • Associative array containing arbitrary (key, response) entries.
  • Exact match key lookup returns hit/miss result and associated response value on hit.
  • High throughput: 150 MLookups/s per HBM/DDR BCAM instance.
  • Flexible: Supports a wide range of key widths, response widths, and lookup rates.
  • Supports all key widths up to 992 bits and all response widths up to 1013 bits.
  • Scalable: Supports one or multiple HBM/DDR BCAM instances, a single instance can use all DRAM within two HBM stacks allowing very large HBM/DDR BCAMs.
  • High storage efficiency: 90% of the DRAM bits are transformed to CAM bits.
  • Supports Error Correction Coding (ECC) by means of HBM configuration.
  • Supports entry insert, delete, and update using highly portable software APIs.
  • Can be inferred from within P4 code using the Xilinx Vitis Networking P4 tool.

Semi-Ternary Content Addressable Memory

  • Associative array containing arbitrary (key, mask, priority, response) entries.
  • Ternary match key lookup returns hit/miss result and associated response value on hit.
  • High throughput: one lookup per clock cycle at 600 MHz.
  • Flexible: supports a wide range of key widths, response widths and lookup rates with optimized resource utilization.
  • Supports all key widths up to 992 bits and all response widths up to 1024 bits.
  • Supports both UltraRAM (URAM) and block RAM implementations.
  • calable: supports one or multiple STCAM instances, each instance can use all of the block RAM/URAM within an SLR allowing very large STCAMs.
  • High storage efficiency, 95% of the RAM bits are transformed to CAM bits.
  • Supports error correction coding (ECC). Single-bit errors are corrected dynamically during lookups, and permanently with scrubbing.
  • Supports Vivado IP integrator.
  • Supports entry insert, delete, update using standard TCAM like software APIs

Ternary Content Addressable Memory

  • Associative array containing arbitrary (key, mask, priority, response) entries.
  • Ternary match key lookup returns hit/miss result and associated response value on hit.
  • High throughput: one lookup per clock cycle at 600 MHz.
  • Flexible, supports a wide range of key widths, response widths and lookup rates with optimized resource utilization.
  • Supports all key widths up to 991 bits and all response widths up to 1024 bits.
  • Up to eight 16-bit wide range comparison fields in each rule minimizes the need for costly rule expansion.
  • Supports both UltraRAM (URAM) and block RAM implementations.
  • Scalable, supports one or multiple TCAM instances, each instance can use all UltraRAM / block RAM within an SLR allowing for very large TCAMs.
  • Supports error correction coding (ECC). Single-bit errors are corrected dynamically during lookups, and permanently with patrol scrubbing.
  • Supports Vivado® IP integrator.
  • Supports entry insert, delete, update using standard TCAM-like software APIs.
  • Can be inferred from within P4 code using Xilinx Vitis Networking P4 tool.

Support

Documentation

Featured Documents

Default Default Title Document Type Date
Part Numbers
Part Number Description
EF-DI-CAM-EXTENDED-PROj LogiCORE,BCAM, STCAM (LPM), TCAM (All) Project License
EF-DI-CAM-EXTENDED-SITE LogiCORE, BCAM, STCAM (LPM), TCAM (All) Site License
EF-DI-CAM-EXTENDED-WW LogiCORE, BCAM, STCAM (LPM), TCAM (All) Worldwide License
EFR-DI-CAM-EXTENDED-PROJ LogiCORE, BCAM, STCAM (LPM), TCAM (All) Project License Support Renewal
EFR-DI-CAM-EXTENDED-SITE LogiCORE, BCAM, STCAM (LPM), TCAM (All), Site License Support Renewal
EFR-DI-CAM-EXTENDED-WW LogiCORE, BCAM, STCAM (LPM), TCAM (All) Worldwide License Support Renewal