Xilinx is now part ofAMDUpdated Privacy Policy

Getting to Link Up with PCI Express in UltraScale+

This video walks through the process of adding three newly available debug features that can be used to help get a PCI Express link up and running and demonstrating how to use the features. The ‘Enable JTAG Debugger’ allows for different state machines in the PCI Express IP to be viewed. ‘In System IBERT’ lets users see eye diagrams based on actual PCI Express traffic and ‘Descrambler for Gen3 Mode’ descrambles data between the PCIe Block and Transceiver in both receive and transmit directions making it easier to debug PCIe link traffic.