Vitis Networking P4 is a high-level design environment to simplify the design of packet-processing data planes that target FPGA hardware. It is a tool to convert the P4 design intent into a Xilinx FPGA design solution. It allows programmers to build new data planes by explicitly specifying the header and packet processing. It supports processing engines with specialized behavior, to include: parsing engines, match-action engines, and deparsing engines, each generated according to an application-specific requirement. To implement a P4 design the compiler maps the control flow onto a custom data plane architecture of engines. This mapping chooses appropriate engine types and customizes each of them based on the P4-specified processing.
Construction of hierarchical Vitis Networking P4 systems, consisting of a large variety of different types of engines including: Parsing, Deparsing, and Match-Action engines
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