Vitis Networking P4


Product Description

Vitis Networking P4 is a high-level design environment to simplify the design of packet-processing data planes that target FPGA hardware. It is a tool to convert the P4 design intent into a Xilinx FPGA design solution. It allows programmers to build new data planes by explicitly specifying the header and packet processing. It supports processing engines with specialized behavior, to include: parsing engines, match-action engines, and deparsing engines, each generated according to an application-specific requirement. To implement a P4 design the compiler maps the control flow onto a custom data plane architecture of engines. This mapping chooses appropriate engine types and customizes each of them based on the P4-specified processing.

Key Features and Benefits

Construction of hierarchical Vitis Networking P4 systems, consisting of a large variety of different types of engines including: Parsing, Deparsing, and Match-Action engines

  • Parsing engines extract header information from packets
  • Deparsing engines manipulate the contents of packet headers by inserting, modifying, or removing packet data
  • Action engines are designed for manipulating metadata that might be determined from packets or data originating externally or internally from some other engine
  • Look-up engines instantiate memory search IP cores generated from a library for packet processing including: exact match (BCAM), longest-prefix match (STCAM), ternary match (TCAM), and RAM (direct) tables
  • Systems resulting in high performance hardware implementations, achieving up to 200 Gb/s
  • Support for different clock domains so that engines can run at one of the following frequencies:
    • Line rate of the packet data bus used typically for engines reading or modifying packets
    • Packet rate used for functions that occur once per packet such as an individual look-up
    • Control rate which is the speed of the memory-mapped control interface for controlling and configuring engines
  • Software available for high level system simulation of the design prior to running RTL simulations
  • System backpressure capability is automatically generated including the insertion of buffers providing dataflow synchronization for engines. This capability enables backpressure of the packet bus for momentarily pausing packet processing
  • AXI-Stream signaling protocol for packet interfaces

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