Adder/Subtracter

Overview

Product Description

The Adder/Subtracter IP provides LUT and single DSP48 slice add/sub implementations. The Adder/Subtracter module can implement adders (A+B), subtracters (A–B), and dynamically configurable adder/subtracters which operate on signed or unsigned data. The function can be implemented in a single DSP48 slice or LUTs. The module can be pipelined.


Key Features and Benefits

  • Generates adder, subtracter and add/subtracter functions
  • Supports two’s complement-signed and unsigned operations
  • Supports fabric implementation inputs ranging from 1 to 256 bits wide
  • Supports DSP48 slice implementation with inputs up to 48 bits wide 
  • Optional carry input and output.
  • Optional clock enable and synchronous clear
  • Optional bypass (loud) capability
  • Option to set the B Value to a constant
  • Optional pipelined operation
  • For use with Xilinx Vivado® IP Catalog, Xilinx AccelDSP™ Synthesis Tool, and Xilinx System Generator.

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