Complex Multiplier

Overview

Product Description

The Xilinx LogiCORE™ Complex Multiplier IP core implements AXI4-Stream compliant, high-performance, optimized complex multipliers based on user-specified options. All operands and the results are represented in signed two’s complement format. The operand widths and the result width are parameterizable.


Key Features and Benefits

  • Support AXI4-stream interface
  • Delivers VHDL demonstration testbench with CORE Generator
  • Supports inputs ranging from 8 to 63 bits wide
  • Supports outputs ranging from 1 to 127 bits wide
  • Supports truncation or unbiased rounding.
  • Option to use LUTs or embedded multipliers  DSP48 slice.
  • Optimization for speed or resource utilization is available through implementation using the 3-multiplier or the 4-multiplier solutions
  • Instantaneous Resource Estimation of  DSP48 slice

Resource Utilization


Support

Documentation

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