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RAM-based Shift Register

Overview

Product Description

The Xilinx LogiCORE™ RAM-based Shift Register IP core generates fast, compact FIFO-like-style registers, delay lines or time-skew buffers using the SRL16/SRL32 mode of the slice LUTs available in Xilinx FPGA devices. Implementing Shift Registers with the SRL16/SRL32 provides large resource and power savings. The IP supports fixed-length or variable-length shift registers.


Key Features and Benefits

  • Generates fast, compact, FIFO-style shift registers or delay lines using the SRL16/SRL32 mode of the slice LUTs
  • User options to create fixed-length or variable-length shift registers
  • Speed or resource optimization for variable length shift registers
  • Optional output register with clock enable and synchronous controls for variable length shift registers

Resource Utilization


Support

Documentation

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