Spartan-3A FPGAs
Spartan-3A FPGAs
Lowest Total Cost. Period.
- The world’s lowest cost I/O optimized FPGAs
- Delivers up to 502 I/Os with support for industry-leading 26 popular and emerging I/O standards
Key Documentation
Quick Links
Videos
-Tang Yimin, General Manager, Beijing Easy Broadband Technology Co. LTD China
The Spartan®-3A FPGA is the world’s lowest cost I/O optimized full feature platform of five devices with system gates ranging from 50K to 1.4M gates, and I/Os ranging from 108 to 502 I/Os, with density migration.
Spartan-3A FPGA Benefits
- Industry’s largest selection of device/package options
- Industry’s most comprehensive IP library
- Leading embedded and DSP solutions
- Efficient, cost-effective board designs
- Allows use of fewer components
- Increased system reliability by eliminating external components
- Unique Device DNA serial number (57-bits) helps prevent design cloning, unauthorized overbuilding and reverse engineering
- Secure mechanism to deliver IP
- Customizable algorithms for security as well as responses to failures
- Integrate MicroBlaze™ soft processor into FPGA and reduce bill-of-material (BOM)
- Reduce obsolescence risks with soft processors
- Reduce inventory cost by using common flexible embedded processing architecture across multiple products
Spartan-3A FPGA Features
Highlighted row indicates key feature.
Dual power management modes for instant power savings and eliminates the need for extra components.
The integrated power management (PDF) reduces power consumption by up to 99%. A single pin activated, hardware feature is built-in unlike other external implementations which requires additional components.
- Over 40% static power reduction
- All states saved in memory
- Scale down voltage (VCCAUX) and shut off non-essential functions (e.g., FPGA inputs, interconnects)
- System synchronization for fast wake-up
- Up to 99% static power reduction
- Shut off all power
- Wake up time
- Ultimate battery life extension
Suspend mode
Hibernate mode
Figure 1
Dual power management modes allow the device to go to an extremely low power state which can reduce power consumption significantly.
Device DNA security for the ultimate flexibility in customizing security solutions for high volume, low-cost systems.
Extended Spartan-3A FPGAs offer the ultimate flexibility in customizing security solutions for high volume, low-cost systems.
- Customizable security algorithms utilizing unique Device DNA
- Monitor JTAG access and take action
- Monitor for tampering and alert for a bitstream alteration
- Ability to increase algorithm complexity
- Hidden bitstream deters bitstream snooping
- Tamper resistant packaging
- JTAG lockdown prevents “backdoor” access
- Readback disable to prevent configuration readback via JTAG or ICAP
Integrated Flash Memory for simple and secure embedded application storage, lockdown and erase features.
This integrated memory can be used for both device configuration as well as a valuable system resource for the user. It provides simple and secure embedded application storage while enabling advanced real-time control with fine-grained protection, lockdown and erase features.
- Simple and secure embedded application storage with up to 11Mb of integrated user Flash
- Enables single-chip board designs for space-conscious applications
- Worry-free configuration
- Twenty year data retention with 100K write cycles
- Pin compatible to the Spartan-3A FPGA platform
XtremeDSP DSP48A Slice for advanced DSP functions.
The Spartan-3A FPGA platform’s optimized DSP48A slice* (PDF) achieves 250 MHz operation in the slowest speed grade and enables advanced DSP functions to derive over 30 GMACS.
- XtremeDSP™ slices providing advanced MACC functionality
- Configurable logic blocks to store data and implement logic functions
- Precise clock management resources
- Advanced I/O structure
- 18-bit by 18-bit, two's complement multiplier with full precision 36-bit result, sign extended to 48 bits
- Pre-adder saves 9 logic slices per DSP48A used
- Two input, flexible 48-bit adder/subtracter with optional registered accumulation feedback
- DSP co-processing functions such as MAC engines, distributed algorithms and fully parallel FIR filters
* Available only in largest two devices.
Embedded processing to reduce obsolescence risk and inventory costs
MicroBlaze™ soft processor delivers inexpensive, highly functional Linux embedded processing.
- Industry’s most versatile, low-cost embedded processing platform
- Integrate processor into FPGA and reduce BOM
- Reduce obsolescence risks with soft processors
- Reduce inventory cost by using common flexible embedded processing architecture across multiple products
Four level memory architecture for optimal granularity and efficient area utilization
Four level memory architecture (PDF) provides the optimal granularity and efficient area utilization.
- Up to 373 K distributed SelectRAM™+ memory
- Each LUT works as a single-port or dual-port RAM/ROM
- LUTs can be cascaded to build larger memories
- Flexible memory for FIFOs, and buffers
- Up to 2.2 M embedded block RAM
- Up to 104 blocks of synchronous 18 Kb block RAM can be cascaded
- Each 18 Kb block can be configured as a single/dual-port RAM
- Supports multiple aspect ratios, data-width conversion and parity
- Up to 16 Mb of integrated Flash memory
- System flexibility with up to 11Mb of on-chip user Flash
- Single-chip solution for failsafe field upgradeability using MultiBoot feature
- New benchmark in non-volatile FPGA market for retention and cycling
- Popular low cost external memory
- Connects low cost memories via interfaces such as HSTL and SSTL
- Large system memory requirements
Table 1
Four level memory architecture
Leading connectivity platform for implementing multiple bridging, differential signaling, and memory interfaces with SelectIO™ technology
Implement multiple bridging, differential signaling, and memory interfaces with SelectIO™ technology.
- Supports most popular and emerging single-ended and differential signaling standards including TMDS, PPDS, SSTL3 Class I and II
- Pre-engineered interface IP solutions including PCI™, PCI Express®, USB, Firewire, CAN, SPI, and I2C
- Advanced interfacing supports up to 26 different single-ended and differential I/O standards
- Full hot-swap compliance and 3.3V support
- 622+ Mb/s data transfer rate per I/O
Figure 1
Extended Spartan-3A FPGAs support multiple platform standards
Configurable logic blocks for wider functionality and less logic levels resulting in higher performance
CLB architecture provides wider functionality and less logic levels resulting in higher performance.
- Four slices per CLB - two each for memory and logic functions.
- Wide-input functions - 16:1 mux in one CLB
- Fast arithmetic functions - two look-ahead carry chains per CLB column
- Four cascadable 16-bit addressable shift registers
- Two slices can be configured as distributed memory
Precise clock management resources for distributing, delaying, multiplying, dividing and phase-shifting clock signals
A self-calibrating, fully digital solution for distributing, delaying, multiplying, dividing and phase-shifting clock signals.
- Up to 8 digital clock managers (DCMs)
- Flexible frequency generation from 5 MHz to 333 MHz
- Precision phase shift control for 0 - 360 degrees
- Fine grain control (1/256 clock period) for clock data synchronization
- Precise 50/50 duty cycle generation
- Up to 9 external outputs available for internal or external usage
Comprehensive configuration capabilities for the broadest flash memory support to allow lowest cost configuration
The broadest flash memory support including Platform Flash, SPI and parallel Flash memories allow lowest cost configuration.
- Platform Flash
- Convenience of a single source supplier for FPGA and flash memory
- Advanced features such as JTAG, bitsteam compression, design revisiton tracking
- High speed programming
- MultiBoot capability allow multiple configurations (PDF)
- Failsafe upgrading
- Application control of the bitstream selection
- replacement of large ASIC or multiple FPGAs with a single Spartan-3 generation FPGA
- Third-party support for parallel, high-speed BPI configuration mode
- Fast parallel configuration speeds
- Easily procured through standard channels
- Commonly found on low-cost systems
- For larger densities, memory can be used for configuration and system functions
Applications and Technologies
Possible applications include
- Embedded processing, DSP, serial connectivity, and parallel connectivity.
- Read this platform's success stories.
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Related Products
Maximize the flexibility of your system and reduce the amount of board space required for your configuration with Configuration Memory for Spartan FPGAs.
Information, products, and services related to Spartan-3A FPGA
Documentation
Data Sheets, User Guides, and Packaging and Pinout Specification
Spartan®-3A FPGA Family Data Sheet
This data sheet provides a summary of the Spartan-3A FPGA family features and specifications.
This guide describes Spartan-3A device pinouts and package specifications; it also includes pinout diagrams and thermal data.
Spartan-3 Generation FPGA User Guide
This document describes the Spartan-3A FPGA family architecture.
This document gives a summary of the Spartan-3A FPGA family.
All Spartan-3A FPGA Documentation
Access all the available documentation for Spartan-3A FPGAs.
Boards
This kit delivers instant access to Spartan-3A FPGA device features such as SUSPEND power-saving mode, high-speed I/O options, DDR2 SDRAM memory interface, commodity flash configuration support, and FPGA/IP protection using Device DNA Security.
The Spartan-3A Platform is perfect for applications where I/O count and capabilities matter more than logic density like bridging, differential signaling and memory interfacing applications, requiring wide or multiple interfaces and modest processing.
Avnet Spartan-3A FPGA Evaluation Kit
The Xilinx Spartan-3A Evaluation Kit provides an easy to use, low cost platform for experimenting and prototyping applications.
Access all the available boards and kits for Spartan-3A FPGAs.
IP
The Memory Interface Generator (MIG) is a free software tool used to generate memory controllers and interfaces for Xilinx® FPGAs.
UMTS/3GPP Turbo Convolutional Encoder
This version of the Turbo Convolutional encoder is designed to meet the 3GPP mobile communication system specification.
CoreConnect™ is an IBM-developed on-chip bus-communications link that enables chip cores from multiple sources to be interconnected to create entire new chips.
Access all the available IP for Spartan-3A FPGAs.
Videos
Lowest Total Cost with Extended Spartan-3A FPGAs
In today's world consumer prices are projected to continue to decline, and now more than ever you need a low cost solution.
Designing Embedded Systems With Linux and Low Cost FPGAs
Learn about the increasing challenges of designing connected embedded systems and how to solve some of them with flexible hardware and software platforms.
Featuring Low Power FPGA and Analog Solutions with Xilinx Extended Spartan-3A FPGA
Learn about on-chip power management modes, power-saving techniques, and power management solution options in Spartan-3 generation FPGAs.
Access all the available videos for Spartan-3A FPGAs.
Training
This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs.
Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® 9.1i tool suite and Xilinx hardware.
Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.
Access all the available training for Spartan-3A FPGAs.
Services and Support
From documentation to tools and IP, Xilinx has the support you need for Spartan-3A FPGA devices.
Configuration Memory for Spartan FPGA
Maximize the flexibility of your system and reduce the amount of board space required for your configuration.
Other
Access the promotional documentation available for Spartan-3A FPGAs.