CoolRunner-II CPLDs Press Backgrounder

Design techniques for electronic systems are constantly changing. In industries at the heart of the digital revolution such as telecommunications, home networking, and wireless communications, this change is especially acute. Functional integration, dramatic increases in complexity, new standards and protocols, and increased time-to-market pressures have bolstered both the design challenges and the architectural opportunities in modern electronic "boxes." One trend driving these changes is the increased integration of core logic with previously discrete functions to achieve lower cost, higher performance, and more compact board designs. Traditionally, ASICs have been the vehicle for such integration but now with the advanced system capabilities and re-programmability, programmable logic devices (PLDs), especially low power Complex Programmable logic (CPLDs), have begun to take on this role in system design.

Until recently, CPLDs had been used primarily as "glue logic," for applications such as state machines and decoding functions that tie various system devices together, acting as a programmable system housekeeper. In these instances, CPLD usage was usually limited to the system periphery. Now, however, the newest generation of CPLDs, which combine high performance, lower power, lower cost, and integration of specialized capabilities, are being used as the re-programmable ASSP (Application Specific Special Purpose) for modern electronic systems. The flexibility and increase in capabilities of the CPLDs, especially given the pressures of greatly compressed product development cycles and rapidly changing standards, have accelerated the use of these devices to simplify core logic in electronic systems.

New Market Pressures: Power and Speed

The previous decade saw an explosion in the number and variety of data/telecom, consumer and portable electronics devices and the capabilities they brought to the market. As portable consumer electronics platforms moved from analog to digital, it became possible to integrate multiple functions into a single product. This feature explosion, combined with reduced costs from process and design advances, has driven intense market demand for small, inexpensive portable consumer products that combined digital audio, video, and data capabilities. This consumer digital convergence of audio, video, and data capabilities has dramatically changed the process of planning, designing, and managing a portfolio of consumer products. In the networking and communication industries, power and heat dissipation have become important design considerations in high-speed datacom and telecom equipment. With ever shrinking box size and increasing performance requirements, the demand for low power devices that delivered high-speed frequency operation and better reliability became extremely important. Product life cycles have been dramatically compressed as new features were added to existing technologies such as PDAs, cell phones and satellite set-top boxes. New technologies such as MP3 players, digital video recorders, and home networks are being consolidated into new consumer electronic platforms. One example could be a combination cell phone, digital camera, and MP3 player. In addition to rapidly shrinking life cycles, new and competing products are introducing a plethora of new and changing interface standards. In portable wireless home networking, for example, competing standards such as Bluetooth, 802.11b, HomeRF, and HiperLAN2 make designing wireless consumer products quite a challenge. In such a rapidly changing market with greatly compressed product life cycles, getting to market early is critical before prices decline and products become obsolete. In addition, making designs flexible enough to grow with changing consumer preferences, evolving standards, and the introduction of competing and complementary technologies can dramatically increase the chances for market success. There is no indication that these levels of product innovation and market pressure will lessen in the coming years. Designers will continue to face the challenge of designing products that can be quickly brought to market and that are flexible enough to evolve with changing market demands. Security will also be a factor in choosing where critical pieces of advanced code reside. A key solution in meeting these intensifying market challenges is the new CoolRunner-II family of CPLDs.

The Real Digital CPLD

Based on a 0.18 µm and 4 or 5-layer metal silicon process (depending on density), the CoolRunner-II CPLD family uses the most advanced process technologies available today. Due to this process migration, die costs have also been optimized. The family's core voltage operation is 1.8 V; CoolRunner-II CPLDs also incorporate I/O technology allowing 1.5, 1.8, 2.5 and 3.3 volt operation. The CoolRunner-II CPLD family will be introduced in densities from 32 to 512 macrocells. The CoolRunner-II CPLD family extends the low power offering of the CoolRunner XPLA3 series by up to 50% in addition to providing higher grade performance (over 300MHz). In addition, CoolRunner-II, has added a variety of advanced system features.

System Features

CoolRunner-II CPLDs deliver advanced system features and low power operation that enable the integration of discrete system functions into a single re-programmable device, resulting in lower costs, higher reliability, faster time to market, and smaller designs.

Advanced Interface Standards Support

The CoolRunner-II advanced I/O interface capability fully addresses all aspects of system connectivity in a wide range of product applications. This solution consists of both the physical interface and the protocols to maximize system interface bandwidth. CoolRunner-II CPLDs provide the fastest and most flexible electrical interface available on a consumer CPLD today. With interfaces like DataGate a programmable on/off switch for power management, and advance interfaces like LVTTL, LVCMOS, HSTL and SSTL, CoolRunner-II CPLDs enable seamless interfaces to external high-performance memories and other logic devices. Another feature incorporated into CoolRunner-II CPLDs is Schmitt trigger inputs (also known as input hysteresis). To ease analog component interface, CoolRunner-II incorporates a Schmitt trigger input to speed transition of signals and reduces power consumption. Schmitt trigger inputs can also be used to form a simple oscillator circuit. This in turn reduces cost by reducing component costs.

Unsurpassed Clock Management

In today's rapidly growing high technology electronic designs, clock management has become increasingly more important to achieve required performance and to reduce power consumption. CoolRunner-II CPLDs address this challenge by providing both clock doubling for improved performance and clock division for power management. By taking a page from microprocessor power reduction, the CoolRunner-II family provides a feature unique to Xilinx called, CoolCLOCK. CoolCLOCK is a combination clock divider and clock doubler that the divides the incoming clock by two and then doubles the clock at the output level to maintain the same performance while reducing the internal power consumption . CoolRunner-II CPLDs give the designer unsurpassed clock management features that enable an easy to implement total clock management solution.

Unprecedented Design Security

Due to the explosion of new applications in the electronics markets, and their highly competitive nature, the need for effective design security has never been greater. System designers need the ability to protect their design codes from unscrupulous competitors. The CoolRunner-II family provides an unprecedented four levels of design security buried within the layers of the device and scattered throughout the die to make their detection virtually impossible. Designers can now design with the knowledge they using the best design security available on any CPLD in the industry.

Advanced Design Tools

The CoolRunner-II solution includes industry-leading design tools. With free ISE WebPACK design software and the Xilinx ISE 4.1i Integrated Software Environment (ISE), CoolRunner-II solutions give the fastest compile times, push-button design performance, and the most rapid time to market of any competing logic solution, all within a streamlined design methodology. The ultra-fast, user friendly ISE 4.1i software supports the entire range of Xilinx programmable products including XC9500 and CoolRunnerTM CPLDs, all Spartan Series cost-optimized FPGAs, and all Virtex-series Platform FPGAs. The software comes in four configurations:

• ISE Foundation - A fully integrated design solution with everything needed to efficiently create, synthesize, verify, and implement your logic design.
• ISE Alliance - A set of Xilinx implementation tools that are designed to seamlessly integrate into your existing design environment.
• ISE WebPACK - A free, downloadable, fully functional version of the software that handles device designs in all Xilinx products except the largest Virtex densities.
• ISE BaseX - An enhanced version of the ISE WebPACK tools that supports the design of additional FPGAs and offers supplementary design capabilities.

Summary

The CoolRunner-II CPLD solution offers unprecedented levels of cost-optimized system integration, bringing advanced system capabilities to cost-sensitive consumer digital products. The CoolRunner-II family also address the requirements of markets as diverse as telecommunications, data communications, and industrial control. The combination of flexibility, features, and extensive web support in a cost-optimized solution is a major advance for designers striving to meet the challenges of the consumer digital convergence market. See www.xilinx.com/cr2 for further information on this unique programmable logic solution.