Product|devboards

 

Spartan-3A Starter Kit Spartan-3AN Starter Kit

  Spartan-3A FPGAs Spartan-3AN FPGAs
 

Home : Products & Services : Development Boards : Spartan-3A/3AN Starter Kit : Spartan-3A/3AN Starter Kit Board Design Examples

Spartan-3A/3AN FPGA Starter Kit Board Design Examples


Below are example designs created for the Spartan®-3A FPGA Starter Kit board and the Spartan-3AN FPGA Starter Kit board to demonstrate various features or capabilities.  Documentation and source files are included.  These example designs are provided with the Limitations described below.

Description
Features Used, Kit Supported
Software Version
Doc
Files

DDR2 MIG Reference Design

DDR2 Memory Interface Design

 

Spartan-3A

ISE® 12.2

-

zip

Demo Design for the Starter Kit Board

This describes the out-of-the box demo design shipped with the board.  Includes how to set up and operate the demonstration, evaluating MultiBoot and Suspend, plus demo technical details.

 

All, PicoBlaze™

Spartan-3A

ISE 9.1i SP1

Spartan-3A

pdf

zip

UCF Constraints File for the Starter Kit Board

This is the complete constraints file for the Starter Kit. This file can be used as the starting point for a user design. The net names are from the initial design but can be replaced with the names for a customer design file. I/O standards match the external connections available on the starter kit board.  

 

VCCAUX, Suspend, I/O locations and standards

Spartan-3A

ISE 9.1i SP1

-

UCF

Restoring Out-of-the-Box Designs

A short overview of what the Starter Kit does "out of the box" and instructions on how to restore the board to the original "out of the box" state. The ZIP file has the "golden" MCS files that are pre-programmed before the board is shipped. The PDF file contains instructions for restoring the board to its original settings using these MCS files in case any of the configuration memories were updated during use.

 

Platform Flash,
SPI Flash, Parallel NOR Flash

Spartan-3A

ISE 9.1i SP1

pdf

zip

Board Verification Test Specification

This is the board test specification and the board test design. This was used during initial board verification and some functions are used during production test. It is provided to enable customers to test a board if something is not working as expected. The design files may also be of general interest. The ZIP file has the design source, a script to run them, and the resulting compiled files.

 

All

Spartan-3A

ISE 9.1i SP1
pdf
zip

Virtual Orchestra Studio

Similar to various music playing games. Players hit keyboard keys when a color block drops to the horizon line. Every key hit produces a sound, and a song is played if every key is hit correctly at the right time.

PicoBlaze

Keyboard input, VGA and Audio output

Spartan-3AN

ISE 10.1

pdf

zip

MultiBoot Trigger

Each Spartan-3AN device contains an internal Flash memory capable of supporting two device configurations. This design provides a macro and illustrates step by step how to implement a system which automatically performs MultiBoot reconfiguration between two configuration images programmed into the XC3S700AN device on the Spartan-3AN FPGA Starter Kit. The optimum MultiBoot trigger macro is also suitable for use in Spartan-3A and Spartan-3A DSP devices. This reference design implements the basic form of MultiBoot which is suitable for many applications. Those interested in using more advanced techniques will find the ‘MultiBoot Control’ reference design of interest. It is recommended that you should be familiar with the board and ISE tools before using this design.

Internal SPI Flash

Spartan-3AN

ISE 10.1

pdf

zip

MultiBoot Control

This design will enable you to experiment with the MultiBoot capability of the Spartan-3A devices using the Internal Configuration Access Port (ICAP). Several configuration images can be stored and initiate a reconfiguration to any other image, which gives rise to the term MultiBoot.

 

PicoBlaze
RS232, SPI Flash

Spartan-3A

ISE 9.2i SP3

pdf

zip

XC3S700AN Flash Programmer

Allows experimenting with the internal Flash memory of the XC3S700AN device on the Spartan-3AN Starter Kit. The 8M-bit memory can hold configuration images for the FPGA and provide general non-volatile storage for other applications. Using a simple terminal program such as HyperTerminal you can use commands to manually program individual bytes or download complete configuration images, or erase pages of the memory, read the memory to verify contents, and display the unique Device DNA and 128-byte security register values.

 

PicoBlaze,
RS232

Spartan-3AN

ISE 9.2i SP2

pdf

zip

Programmer for the Atmel AT45DB161D SPI Flash

This design transforms the FPGA into a programmer for the 16M-bit (2M-byte) Atmel AT45DB161D DataFlash SPI memory which can be used to hold configuration images for the Spartan device as well provide general nonvolatile storage for other applications implemented within the FPGA. Using a simple terminal program you can manually program individual bytes or download complete configuration images using UFP files, erase pages of the memory, read the memory to verify contents, and display the device identifier and 128-byte security register value.

 

PicoBlaze
RS232, SPI Flash

Spartan-3A

ISE 9.1i SP1

pdf

zip

Programmer for the ST Microelectronics M29DW323DT Parallel NOR Flash Using PicoBlaze Processor

This design transforms the FPGA into a programmer for the 4M-byte ST Microelectronics M29DW323DT Parallel Flash memory which can be used to hold configuration images for the FPGA as well provide general nonvolatile storage for other applications implemented within the FPGA. Using a simple terminal program you can manually program individual bytes or download complete configuration images using standard MCS files, erase the memory in part or in full, read the memory to verify contents, and display the device identifier and 64-bit unique device numbers.

 

PicoBlaze,
RS232, Parallel NOR Flash

Spartan-3A

ISE 9.1i SP1

pdf

zip

Programmer for the Parallel NOR Flash Using MicroBlaze Processor

This design transforms the FPGA into a programmer for the 4M-byte Parallel Flash memory. The system contains the MicroBlaze™ processor v6 running at 50 MHz, LMB Block RAM (32KB), OPB EMC Controller for BPI Flash (4MB), and a Hardware Debug Module.

 

MicroBlaze,
Parallel NOR Flash

Spartan-3A

ISE 9.1i SP3,
EDK 9.1i SP2

readme

zip

Device DNA Reader

This design employs a PicoBlaze processor to read the unique ‘DNA’ value embedded in each FPGA and display it on the LCD screen. The signals associated with reading the ‘DNA_PORT’ are also made available for observation at the ‘J2’ connector. The documentation describes both the reading of the DNA value and the control of the LCD display in adequate detail for use in your own designs.

 

PicoBlaze,
LCD, LEDs

Spartan-3A

ISE 9.1i SP1
pdf
zip

MicroBlaze Reference Design - Web Server

This MicroBlaze processor reference design includes the Web Server application from XAPP433. The design includes interfaces to many of the components on the board, including the DDR2 SDRAM, NOR Flash, LCD, RS232, and switches. The design includes a custom LCD core, custom rotary switch core, and a custom ICAP core for MultiBoot from the MicroBlaze processor.

 

MicroBlaze,
Ethernet, DDR Memory, Parallel NOR Flash, RS232, LCD, LEDs

Spartan-3A

ISE 9.1i EDK 9.1i
pdf
zip

Paint Demo

Requires the Spartan-3AN FPGA Starter Kit.

This design demonstrates using the Spartan-3AN FPGA In-System Flash for configuration and user data. The design implements a simple paint program by allowing drawing and control with a mouse.The initial internal flash programming includes seven pre-stored pictures which can be edited and re-written.

 

Spartan-3AN
In-System Flash, PicoBlaze,
PS/2 mouse port, VGA port

Spartan-3AN

ISE 9.1i SP3
pdf
zip

LVDS Demonstration

Uses the ChipScope™ analyzer to help check high speed LVDS performance and debug DCM operation using the low cost J2/J15 connectors without extensive oscilloscope setup. Highlights XAPP485 and XAPP486 serdes applications.

ChipScope Pro Analyzer, LVDS, connectors

Spartan-3A

ISE 9.1i
pdf
zip

DDR2 Demonstration

Live DDR2 video frame buffer demo with a UXGA image display. Requires a UXGA monitor with a VGA port. bitmap.mcs is programmed into the parallel NOR flash using the design above, while a second FPGA programming file for Platform Flash (framebuf_routed.mcs) moves the image to DDR2 memory and displays it at 400 Mb/s through the analog VGA output port.

DDR400, Platform Flash,
Parallel NOR Flash, VGA

Spartan-3A

ISE 9.2.01i

pdf

(XAPP
458)

zip

Security Demonstration

• Reads a Device DNA value
• Generates a check value and stores in non-volatile memory
• Runs a security algorithm
• Verifies and compares the result to the check value
• Indicates various response examples

Device DNA, Parallel and SPI Flash, VGA port

Spartan-3A, Spartan-3AN

ISE 9.2i
zip

Practical Power Testing

Enables a variety of experiments to accurately determine the power requirements of a Spartan XC3S700A device. Shows how to measure quiescent current of both unconfigured and configured states and compare with the power saving Suspend mode. Investigates power dissipation of features including counters, memories and multipliers. Results provide real power figures to compare with theoretical models and estimation tools. Anyone developing products for which low power is important should find that the practical knowledge obtained from conducting these experiments will be of particular use when implementing their design. The first time Starter Kit user should begin with the 'Demo Design for the Starter Kit Board’ reference design at the top of the page.

PicoBlaze,
RS232

Spartan-3A

ISE 9.2i SP4

pdf

zip

DDR2 Back-to-Back Bursts Wrapper

MIG wrapper with easy FIFO-like user interface, suitable for applications such as Video Line buffer access

DDR2 Memory, ChipScope™ Pro

Spartan-3A, Spartan-3AN

ISE 11.2
pdf
zip

Limited Warranty and Disclaimer. These designs are provided to you “as is”.  Xilinx and its licensors make and you receive no warranties or conditions, express, implied, statutory or otherwise, and Xilinx specifically disclaims any implied warranties of merchantability, non-infringement, or fitness for a particular purpose.  Xilinx does not warrant that the functions contained in these designs will meet your requirements, or that the operation of these designs will be uninterrupted or error free, or that defects in the Designs will be corrected.  Furthermore, Xilinx does not warrant or make any representations regarding use or the results of the use of the designs in terms of correctness, accuracy, reliability, or otherwise.

Limitation of Liability.  In no event will Xilinx or its licensors be liable for any loss of data, lost profits, cost or procurement of substitute goods or services, or for any special, incidental, consequential, or indirect damages arising from the use or operation of the designs or accompanying documentation, however caused and on any theory of liability.  This limitation will apply even if Xilinx has been advised of the possibility of such damage.  This limitation shall apply notwithstanding the failure of the essential purpose of any limited remedies herein.

These design modules are not supported by Xilinx Technical support as an official Xilinx Product.

/csi/footer.htm