Vivado Debug offers a variety of solutions to help users debug their designs easily, quickly, and more effectively. These solutions consist of tools, IPs, and flows that enable a wide range of capabilities from logic to system level debug while the user design is running in hardware.
In addition, Vivado provides a unified design environment that enables you to perform different debug tasks within the same IDE in which interfaces look consistent and features communicate well between each other.
What’s New in 2018.3
Debug Flows - added support for preserving enumerated FSM states in RTL:
- User can now add mark_debug to enumerated FSM states in RTL. The debug flow preserves the enumeration throughout the implementation and allows user to view it during debug in the Waveform window.
Programming - added support for indirect programming of low-density ISSI serial NOR Flash memories.
Tools & Features
As part of Vivado IDE, Hardware Manger enables user to program the device and debug the design after bitstream generation. Using Hardware Manger, users connect and program hardware targets containing one or more FPGA devices and then interact with debug IPs in designs via Tcl or GUI interfaces including Logic Analyzer, Serial I/O Analyzer, and Memory Calibration Debug.
- Device programmer for FPGA, configuration memory devices, eFUSE AES key/registers
- Access to System Monitor (SYSMON) - ADC & on-chip sensors
- Tcl scripting support for debug automation
- Basic remote debugging over network via hw_server
- Advanced remote debugging using Xilinx Virtual Cable (XVC)
Vivado Lab Edition – HW Manager and all of its features are available as part of the Vivado Design Edition or as a standalone installation package called Vivado Lab Edition. This edition has a small install package size (~1GB) with a small disk footprint (~2.4GB) after installation. It is typically used for lab environment settings that have limited disk space, memory, or connectivity. For more information, go to Vivado downloads and installation page.
Vivado provides various debug IP and tool features that enable you to easily perform in-system logic debugging of your implemented design.
- ILA – used for triggering on events and capturing the data from internal signals
- System ILA - used for transaction-level debug of AXI interfaces
- VIO – used for monitoring and driving internal signals
- JTAG-to-AXI – used for direct interaction with AXI interfaces via Tcl
Different debug flows in the tool enable you to easily add or set up these debug IPs within your design at your preferred stage of the design cycle.
After the device is programmed, you then interact with these IPs in HW Manager by using the Vivado Logic Analyzer tool. Different dashboards within the Logic Analyzer tool display the status and control the operation of logic debug IPs.
- Intuitive and productive debug flows & methodology
- Support for identifying debug nets in RTL, GUI, XDC
- Netlist insertion support for adding an ILA to a design after synthesis
- HDL instantiation support for all debug IPs
- Support for advanced debug flows (ECO, Incremental) for more debug turns per day
- Support for preserving debug nets/interfaces during synthesis & implementation
- IPI debug flow for transaction-level debug of interfaces
- Flexible analysis tool – Vivado Logic Analyzer
- Customizable dashboards to interact with ILA/VIO
- Easy setup for taking measurements and capturing data
- Configurable Waveform viewer to analyze captured data
AXI Transaction-level Debug – within Vivado IP Integrator (IPI) tool, it is also possible to debug AXI interfaces at transaction-level. IPI makes it easy to debug various interface and signal and provides automation to connect these interfaces to System ILA. Interface information is then preserved throughout the implementation flow and at runtime, Waveform window shows all transaction and events for AXI interfaces based on the issued AXI read/write transfers.
Vivado offers you a fast and easy method to debug and optimize FPGA transceivers. This solution includes a customizable debug IP (IBERT) and Vivado Serial I/O Analyzer tool. Used together, you can take bit-error ratio (BER) measurements on multiple channels, perform 1D/2D eye scans, and adjust transceiver parameters in real-time while your serial I/O channels interact with the rest of the system.
Designed for PMA evaluation and demonstration of transceivers, IBERT also includes data pattern generators and checkers as well as access to transceivers DRP ports. Once IBERT is implemented within the FPGA, Vivado Serial I/O Analyzer interacts with the IP and allows you to create links (analogous to a channel on a board) and analyze the margin of the links by running scans and viewing the results graphically.
- RX Margin Analysis with different scan algorithms
- Link-based analyzer with support for creating custom links
- Link auto-detection
- Link sweep automation for running multiple scan with different settings
- Auto sweep of transceiver parameters in real-time
In-System IBERT – this IP is intended for evaluating & monitoring of UltraScale/UltraScale+ transceivers within a user design. It is capable of utilizing the actual data from the user design running on the FPGA to plot the eye scan of transceivers. It is available in IP catalog as a standalone IP to be used alongside transceiver-based Xilinx IPs. Users can also automatically add this IP to the GT Wizard example design as well as PCIe Gen3 IP.
Memory Calibration Debug tool allows you to quickly debug calibration or data errors in UltraScale/UltraScale+ memory interfaces (DDR4/3, RLDRAM3, QDRII+, and LPDDR3). You can always view and analyze core configuration, calibration status, and data margin of the memory interfaces at any time throughout operation in hardware.
To debug calibration errors, you can use the displayed information to determine which stage of calibration is failing, which byte/nibble/bit is causing the failure, and how the calibration algorithm is failing. In addition, you can analyze the available read margin during normal operation. Observing the margin on each bit helps one determine if there are some signal integrity or board issues on certain data bits.
FPGA debug is typically done via JTAG cable connected to the JTAG pins of the target FPGA device or board. However, this is not always the most efficient way of debugging an FPGA design. Remote debugging offers capabilities that allows FPGA debug without access to physical JTAG pins.
Xilinx Virtual Cable (XVC) solution is a TCP/IP-based protocol that acts like a JTAG cable and provides a way to access and debug your FPGA or SoC design without using a physical cable. XVC solution has both hardware and software components:
- XVC Server is the software component – it implements a TCP/IP protocol to communicate with hw_server and FPGA via TCP/IP socket. It usually runs on an external processor, Host PC, or embedded processor inside the FPGA (Zynq/MPSoC). XAPP1251 shows how to run XVC server on a Zynq device using PetaLinux. XVC protocol specification and example designs are available on Github.
- Debug Bridge is the hardware component – this Xilinx IP offers different modes of connectivity between the external interfaces and other debug IPs. It requires direct user instantiation within the FPGA design.
XVC solution supports many capabilities that can enhance and augment the solution based on user needs such as:
- MDM support to allow debug of MicroBlaze systems via SDK
- Support for dynamic switching between JTAG cable and XVC
- Support for debugging inside Reconfigurable Partitions
- Ability to create separate debug networks for controlling access to debug IPs
Debug over PCIe
In data center applications, FPGA is only connected to a PCIe Host system via PCIe link without any other connection to the hardware device. XVC solution enables users to perform debug over a PCIe link rather than the standard JTAG debug interface.
The main components in a debug over PCIe application are shown below:
- A PCIe design with added XVC capability runs inside the FPGA. The XVC capability is basically connecting the Debug Bridge IP to the PCIe block interface.
- On the software side, Host PC is running the XVC server along with an updated PCIe driver with XVC capability to connect the FPGA.
- Once these components are in place, Vivado software can communicate to the PCIe system by running hw_server either locally on the Host PC or remotely.
The complete solution is provided in the example design of UltraScale/UltraScale+ PCIe Block IP. For more information, refer to product guides for UltraScale Gen3 PCIe Block (PG156) and UltraScale+ PCIe Block (PG213).