Accelerating the development of smarter systems requires levels of automation that go beyond RTL level design. With the introduction of the Vivado™ Design Suite, Xilinx delivers a SoC-strength, IP-and system centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation

Learn more about the value and productivity  Vivado brings to system-level design.

What's New

The Vivado 2013.1 release includes early access release of the IP Integrator, a new IP-centric design flow for accelerating the time to system integration. To obtain a license please contact your local sales office. Please review the release notes for all the latest release information.

What design teams are saying about the Vivado Design Suite

See how the Vivado Design Suite is enabling and accelerating the design cycle from the view of our customers on the Vivado Buzz page.

Accelerating Time IP Creation and Integration

• As the leading provider of Electronic System Level Design tools for All Programmable solutions, Vivado Design Suite System Edition provides Vivado High-Level Synthesis for C, C++ and SystemC, and MATLAB/Simulink based System Generator for DSP. These solutions enable high-level IP specifications to be directly synthesized into VHDL and Verilog accelerating IP verification over 100X and RTL creation by up to 4X. The highly integrated tools can be used individually or in combination with the result being reusable IP for use in the Vivado Design Suite.
• Architected to accelerate IP integration by 4X, Vivado Design Suite’s IP Integrator, IP packager, IP catalog leverage industry standards to streamline accurate assembly reuse of IP at the interface level, dramatically reducing development time. 
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Time to Verification

• Verification of All Programmable devices requires state of the industry solutions. The Vivado simulator provides mixed VHDL / Verilog simulation which is 3X faster than solutions provide by other FPGA vendors.
•  The Vivado Logic Analyzer inserts logic analyzer, system analyzer, and virtual I/O low-profile cores directly into the design, allowing review of any internal signal.
• Extensive cross-probing between design sources, schematic views, hierarchy browsers, design reports, messages, floor plan and device editor views enables faster debug and timing closure by providing graphical feedback to identify design issues at each phase of design.
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Time to Implementation

• Vivado timing driven synthesis leverages Synopsys Design Constraints (SDC) and supports VHDL, Verilog and SystemVerilog.
• Vivado implementation supports hierarchical design flows which enable team design, out-of-context design reuse, and partial reconfiguration providing up to 4X faster time to implementation through state of the industry analytical place-and-route technology.
• With Vivado design editor and incremental flows, a designer has the ability to make ECO changes late in the design cycle that save over 3X versus a complete design iteration.
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Delivering Improved Quality of Results and Resource Utilization

• The Vivado Design Suite together with 7 series All Programmable FPGAs delivers up to 3 speed grade performance advantage and ~35% average power advantage at same performance. In addition, many more designs are significantly easier to route, with LUT utilizations >20% better than the competitive solutions.