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Xilinx's Verification IP (VIP) portfolio provides users with the ability to verify and debug their designs in a simulation environment easily, quickly, and more effectively. Verification IP cores are purpose built verification models whose goal is to ensure correct interoperability and system behavior. Companies in the EDA industry develop VIP for standards based interfaces (AXI, PCIe, SAS, SATA, USB, HDMI, ENET, etc..). Advantages to using VIP include improved design quality and reduced schedule time due to re-usability.

Xilinx's VIP cores are SystemVerilog based simulation models that provide full AXI protocol checking with ARM licensed assertions, support all major simulators, and are included in Vivado at no cost. Xilinx provides VIP for use in designs that use AXI component level (AXI-MM, AXI_Stream) and Processing System(Zynq®-7000) designs.

AXI Verification IP

  • Supports AXI3, AXI4 and AXI-Lite Protocols
  • Supports all protocol data widths and address widths, transfer types and responses
  • Full AXI Protocol Checker support
  • Integrated ARM Licensed Protocol Assertions
  • Transaction level protocol checking (burst type, length, size, lock type, cache type)
  • Configurable as Master, Slave or Passthrough modes of operation

AXI Stream Verification IP

  • Supports AXI4-Stream Protocol
  • Supports all protocol data widths and address widths, transfer types and responses
  • Full AXI Stream Protocol Checker support
  • Integrated ARM Licensed Protocol Assertions
  • Transaction level protocol checking (burst type, length, size, lock type, cache type)
  • Configurable as Master, Slave or Passthrough modes of operation

Zynq-7000 Verification IP

  • Allows for AXI transaction verification for Programmable Logic to Processor System interfaces
  • Drop in replacement for Zynq-7000 BFM
  • Full AXI Protocol Checking
  • Supports AXI3 Protocol
  • Integrated ARM Licensed Protocol Assertions
  • Supports all 9 of the Zynq-7000 AXI interfaces
  • Task based API for transaction programming
  • 32/64–bit Data-width for AXI_HP, 32-bit for AXI_GP and 64-bit for AXI_ACP (Accelerator Cache Coherence Port)

What's New in Vivado 2017.2

AXI Stream Verification IP – Provides full AXI Stream Protocol checking using ARM licensed assertions:

  • AXI4 Stream Master, Slave or Passthrough/Monitor modes of operation
  • Support runtime modes of operation including master, slave and slave memory model
  • Unencrypted SystemVerilog
  • Synthesizes to wires

What’s New in Vivado 2017.1

AXI Verification IP – Provides full AXI Protocol checking using ARM licensed assertions:

  • AXI4 Master, Slave or Passthrough/Monitor modes of operation
  • Support runtime modes of operation including master, slave and slave memory model
  • Unencrypted SystemVerilog
  • Synthesizes to wires

Zynq-7000 Verification IP - Provides simulation model of Zynq-7000 processing system

  • Ease of use via API based programming
  • Allows driving transactions on AXI Master and AXI Slave ports
  • Replaces the Zynq-7000 BFM
  • Example simulation testbench to acclimate users
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