ML505

This application note illustrates how to measure the network performance of the XPS LocalLink Tri Mode Ethernet MAC (TEMAC) in an embedded processor system running the Treck TCP/IP stack.

Design File(s):

• xapp1043_mb.zip
• xapp1043_ppc405.zip

Post-Configuration Access to SPI Flash Memory with Virtex®-5 FPGAs.

This user guide introduces several designs that demonstrate Virtex®-5 device features using the ML505 (LXT), ML506 (SXT), and ML507 (FXT) Evaluation Platforms. The provided designs include processing systems based on the embedded PowerPC® 440 processor block, the MicroBlaze™ soft processor, the integrated Tri-mode Ethernet MAC, and the RocketIO™ GTP or GTX transceiver.

Design File(s):

• ML507 designs
• ML506 designs
• ML505 designs

The ML505/ML506/ML507 Getting Started Tutorial provides step-by-step instructions for setting up and using the Virtex®-5 ML505, ML506, and ML507 Evaluation Platforms. These boards come with a number of pre-installed demonstrations. This tutorial guides you through these demonstrations and provides instructions to run them on the ML50x boards.

Design File(s):

• ML507 docs
• ML506 docs
• ML505 docs

The ML50x boards enable designers to investigate and experiment with features of Virtex®-5 FPGAs. This user guide describes the features and operation of the ML505 (LXT), ML506 (SXT), and ML507 (FXT) Evaluation Platforms.

Design File(s):

• ML507 docs
• ML506 docs
• ML505 docs

This is the PDF for ML505, ML506, and ML507 schematics. The PCB files (Allegro 15.x) and schematic source files (Viewdraw) are accessible from the link below.

Design File(s):

• ML507 docs
• ML506 docs
• ML505 docs

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML505 Embedded Development Platform.

Design File(s):

• Design File for XAPP1030

This guide provides a Video Over IP overview. It discusses the ASI to IP Bridge and the IP to ASI Bridge.