Empowers RTL Designers with Faster Verification and Design Iteration
The Vitis™ HLS tool allows users to easily create complex FPGA algorithms by synthesizing a C/C++ function into RTL. The Vitis HLS tool is tightly integrated with both the Vivado™ Design Suite for synthesis and place & route and the Vitis™ unified software platform for heterogenous system designs and applications.
- Using the Vitis HLS flow, users can apply directives to the C code to create the RTL specific to a desired implementation.
- Multiple design architectures can be created from the C source code and a path for high-quality, correct-by-construction RTL is enabled.
- C simulation can be used to validate the design and allows faster iterations than a traditional RTL-based simulation.
- The Vitis HLS tool features a rich set of analysis and debugging tools that facilitate design optimization.
Vitis HLS for intuitive design and productivity
Programming Model
Vitis HLS Programming Model
Vitis™ HLS C code is geared towards taking advantage of the benefits and characteristics offered by the architecture of AMD FPGAs.
The Vitis HLS tool supports parallel programming constructs in order to model a desired implementation. These constructs include:
- HLS tasks that allow process-level concurrency
- HLS vectors that allow data-level parallelism
- HLS streams that allow communication between concurrent tasks
- Synthesis pragmas can be used to control the results. These pragmas include pipeline, unroll, array partitioning, and interface protocols.
- For additional details, see the "HLS Programmers Guide” section in the Vitis High-Level Synthesis User Guide.
C-to-RTL Conversion
The Vitis HLS tool synthesizes different parts of C code differently:
- Top-level function arguments of the C/C++ code are synthesized into RTL I/O ports and are automatically implemented with an interface synthesis hardware protocol.
- Other C functions are synthesized to RTL blocks—maintaining the design hierarchy.
- C function loops are kept rolled or pipelined to improve performance.
- Arrays in the C code can be targeted to any memory resource, such as BRAM, LUTRAM, and URAM.
- Performance metrics, such as latency, initiation interval, loop iteration latency, and resource utilization, can be reviewed with synthesis reports.
- Vitis HLS tool pragmas and optimization directives allow for configuring the synthesis results for the C/C++ code.
C to RTL Synthesis
Simulation and Verification
Simulation and Verification
The Vitis HLS tool has built-in simulation flows to enable faster verification times:
- C simulation validates the functionality of the C code. This step is fast and uses a C test bench.
- C/RTL co-simulation reuses the C test bench to perform validation on the generated RTL—verifying that the RTL is functionally identical to the C source code.
- The flow has integrated analysis, debug, and waveform viewing capabilities as well as popular simulator support.
IP Export
The output of the Vitis HLS tool is an RTL implementation that can be either packaged into a compiled object file (.xo) or exported to an RTL IP:
- Compiled object files (.xo) is used to create hardware acceleration functions for use in the Vitis application development flow.
- RTL IP can be used in three ways:
- Added using the Vivado™ IP integrator tool
- Imported as an RTL block in the Vivado IDE
- Used as a single blockset in Vitis Model Composer for DSP applications
IP Export
2023.2 Release Highlights
- New Vitis™ Unified IDE for HLS components
- New Vitis HLS license requirements
- New code analyzer feature for obtaining performance estimations before running C synthesis
- Enhancements to AXI interface:
- Enhancements to HLS AXI Stream side-channel support
- Support for user-configurable AXI master caching
- Other enhancements:
- New code complexity report to enable identifying design size issues during C synthesis
- Compile time improvements: Average compile time improvement of 20% in 2023.2 compared to 2023.1*
*Based on testing on August 10, 2023, across 1000 Vitis L2/L3 code library designs, with Vitis HLS release 2023.2 vs. Vitis HLS 2023.1. System configuration during testing: Intel Xeon E5-2690 v4 @ 2.6GHz CPU, 256GB RAM, RedHat Enterprise Linux 8.6. Actual performance will vary. System manufacturers may vary configuration, yielding different results. -VGL-04
2023.1 Release Highlights
- Performance improvements*: Average latency improvements of 5.2% in 2023.1 compared to 2022.2
- Easy way to download, view, and instantiate L1 libraries functions in the Vitis HLS tool. Watch video
- Enhanced support for AXI transactions and burst reporting within the Vitis HLS tool
*The benchmark tests were performed on all 1208 Vitis L1 library C-code designs as of February 12th, 2023. All designs were run using a system with 2P Intel Xeon E5-2690 CPUs with CentOS Linux, SMT enabled, Turbo Boost disabled. Hardware configuration not expected to effect software test results. Results may vary based on software and firmware settings and configurations- VGL-03
2022.2 Release Highlights
- New way to write “task-level parallel” code for data processing applications
- User can explicitly define task-level parallelism using the new hls::task function
- Easier to model for purely streaming designs (e.g., packet switching)
- Performance and timing enhancements
- Tool automatically infers unroll, pipeline, array partitions, and inline pragmas for better performance
- Analysis and debug enhancements
- New feature to synthesize print statements from C source in the generated RTL code
- When RTL is simulated, this allows tracing the execution of a code block and the value of a variable
- Ease of use
- hls::stream interface is now supported for FFT and FIR IPs
2022.1 Release Highlights
- New Timeline Trace Viewer
- Shows the runtime profile of all surviving functions in your design - i.e., those that get converted into modules
- Especially useful to see the behavior of dataflow regions after Co-simulation. Native to Vitis™ HLS - No need to launch the xsim waveform viewer anymore
- New Performance pragma
- HLS what your throughput target is using #pragma hls performance
- HLS will attempt to meet target, if possible, using fewest resources
- HLS will indicate transformations performed, and if it can’t meet target will indicate limiting factor
- Array partition support for Stream of Blocks type
- hls::stream enhancement where each element is an array
- Can be used to break up large array processing into smaller, pipelined pieces
2021.2 Release Highlights
- User Controlled Burst Inference
- User can adopt newly introduced manual burst optimization
- A new class 'hls::burst_maxi’ is added to support manual controlling burst behavior New HLS APIs are provided to use together with the new class.
- Users need to understand AXI AMBA protocol and the hardware transaction level modeling in HLS design
- Timing and QoR Enhancements
- Improve HLS timing estimation accuracy. When HLS reports timing closure, Vivado™ RTL synthesis should also expect to meet timing
- EoU Enhancements
- Add interface adaptors report in the C-synthesis report
- Users need to know the resource impact that interface adaptors have on their design
- Interface adaptors have variable properties that impact design QoR
- Add new section in synthesis report to show list of pragmas and warnings on pragmas
- Analysis and Reporting enhancements
- New mouse drag based zoom in and out capability
- New Overview feature that shows the full graph and allows the user to zoom in on parts of the overall graph
- All functions and loops are shown along with their simulation data
- A new Timeline Trace Viewer is now available after simulation. This viewer shows the runtime profile of your design and allows the user to remain in the Vitis HLS GUI
2021.1 Release Highlights
- New “Flow Navigator” in GUI for quick access to flow phases and reports. The contextual "synthesis, analysis, debug" views are merged into a general default context
- New synthesis report section for the BIND_OP and BIND_STORAGE directives
- A new post synthesis text report reflects the information provided in the GUI synthesis report
- The IP export and Vivado™ implementation run widgets have been redesigned with options to pass settings and constraint files to Vivado
- New function call graph viewer to visualize functions and loops which can be highlighted with an optional heatmap to detect II, latency or DSP/BRAM utilization hot spots
- Versal™ timing calibration and new controls for DSP block native floating-point operations (the -precision option for config_op)
- Alternate flushable pipeline option has been improved (free-running pipeline aka "frp")
- In Vitis, reshaping m_axi interfaces should be done via the hls::vector types
- New customization options for s_axilite and m_axi data storage which can be "auto, "uram", "bram" or "lutram" allowing you to tweak RAM utilization in your design
- In Vitis, introducing a new continuously (aka "never-ending") running mode for kernel
- The axi_lite secondary clock option has been re-instated
The Emeraude Research Team from INSA Lyon, is working on developing new signal processing techniques for embedded audio systems. The team has implemented an ultra-low latency audio DSP program using the AMD Vitis HLS tool. Click here to learn more about how the Vitis HLS tool helped the team to achieve ultra-low latency in an audio DSP-to-FPGA compilation.
Customer Case Study
Achieve Ultra-Low Latency in an Audio DSP-to-FPGA with Vitis HLS
The Emeraude Research Team from INSA Lyon, is working on developing new signal processing techniques for embedded audio systems. The team has implemented an ultra-low latency audio DSP program using the AMD Vitis HLS tool. Click here to learn more about how the Vitis HLS tool helped the team to achieve ultra-low latency in an audio DSP-to-FPGA compilation.
Customer Case Study
Faster Design Space Exploration with Vitis HLS
"The main advantage of the AMD Vitis™ HLS tool, from my perspective, is the design space exploration feature. You can generate different architectures and implementations in a reasonable amount of time by using optimization directives (pipelining, unrolling, etc.). This cannot be done if you code manually with VHDL/Verilog. A nice feature of Vitis HLS is the possibility to do a co-simulation and validation of the HDL-code in order to be sure that the HDL-code is functionally correct." Dr. Frank Kesel - Professor at the University of Pforzheim, Germany
Customer Case Study
