Product Description

HDL Coder™ generates portable, synthesizable VHDL® and Verilog® code from MATLAB® functions, Simulink® models, and Stateflow® charts. The generated HDL code can be used with all AMD FPGAs and Zynq SoCs and generated IP cores can be imported into Vivado IP Integrator.

HDL Coder provides a Workflow Advisor that automates code generation and deployment to a number of FPGA and Zynq development platforms for IP core generation and FPGA in the loop (FIL) operation . You can control HDL architecture and implementation, highlight critical paths, and generate hardware resource utilization estimates. HDL Coder provides traceability between your Simulink model and the generated HDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.