Product Description
The 800G High Speed Ethernet PCS IP core implements the physical coding sublayer (PCS) of the Draft Standard for Ethernet, Amendment: Media Access Control Parameters for 800 Gb/s and Physical Layers and Management Parameters for 400 Gb/s and 800 Gb/s Operation (IEEE P802.3df/D2.0, February 17, 2023) and the Ethernet Technology Consortium 800G Specification (Revision 1.1).
Key Features and Benefits
- Designed to the Ethernet requirements for 800 Gb/s operation specified in the Draft Standard for Ethernet, Amendment: Media Access Control Parameters for 800 Gb/s and Physical Layers and Management Parameters for 400 Gb/s and 800 Gb/s Operation (IEEE P802.3df/D2.0, February 17, 2023) and the Ethernet Technology Consortium 800G Specification (Revision 1.1).
- Supports a total bandwidth of 800 Gb/s
- Supports standalone PCS with RS-FEC
- Supports lane reordering among the 32 PCS lanes
- Status signals for all major functional indicators
- Leverages two hard DCMAC PCS and FEC IP
- Delivered with a top-level wrapper including functional transceiver wrapper, IP netlist, sample test scripts, and AMD Vivado™ Design Suite compile scripts
- Implements an 8-lane interface to connect directly to optical modules using 8 x 106.25 Gb/s SerDes