A sophisticated architecture and design process for Functional Safety applications integrated in FPGA and SoC FPGA can reduce customers’ risks and increase time to revenue and profits significantly. Xilinx provides proven tools with their functional certified Vivado® Design Suite. In combination with Xilinx’s FPGAs and SoCs, the industry’s most reliable products in this field, and pre-approved architectures and design methods, customers can quickly incorporate functional safety in their products with fast development times.
With the architectural features of FPGAs, APSoCs and MPSoCs from Xilinx, the isolation of blocks for redundancy / diversity and for diagnosis can easily be achieved within a single chip solution. Detailed reliability reports for these products provide info for most accurate calculation of a products FIT rate. IP designed in these devices continuously monitor the functional correctness of the device configuration. Dependent on the selected architectures, safety integrity levels up to SIL3 and ASIL D can be achieved.
|Design Examples||Description||Device Support|
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|Design With All Programmable SoC
With two Zynq-7000 devices, a safe design with redundancy in a 1oo2 or 1oo2D architecture can be achieved. Cross monitoring with split voter functions in the FPGA part of Zynq-7000 allows reliable coverage. The implementation of Diagnostic Libraries (STL) enables the design for the targeted safety level.
|All Programmable SoC|
For FPGA designers looking to shorten design time and ensure scalability and re-use, Xilinx provides a comprehensive suite of solutions ranging from C-based design abstractions to IP plug-and-play to address bottlenecks in hardware development, system-level integration, and implementation.