With the Wireless Trend of Densification, CRAN activity and Small Cell deployment for better coverage, the Fronthaul link is challenged both in Bandwidth (BW) and being able to service the heterogeneous networks being deployed. Xilinx offer solutions around switching needs to service the large number of remote radio heads (RRH) by the Baseband processing unit (IQ switching), a lightweight Ethernet switch for servicing a small number of RRH daisy chained or otherwise connected together, as well as IQ compression to effectively increase the Fronthaul bandwidth without using additional Fiber or other techniques.
Proof of Concept Summary
This Proof of Concept design provides a 16 port (8x8) IQ Switch for use in CPRI based wireless systems. The switch is implemented as a 4x4 array which is double clocked to provide 8 ingress and 8 egress ports. Two instances of the 8x8 switch will provide a complete uplink and downlink, any port to any port system.
- 8 Ingress and Egress ports
- Any Ingress port can be routed to any Egress port
- Operates up to CPRI Rate 8 (10.137Gps)
- 32 bit Ingress and Egress port data width
- The switch operates internally at up to 614.4MHz (2x CPRI rate 8 frequency) to provide an 8x8 switch while internally implementing a 4x4 switch to reduce logic usage
- Maximum of 256 time slots per internal port to provide support for rates beyond CPRI Rate 8 (1 Basic Frame = 80 time slots at Line Rate 8)
- Double banking of data & routing table to allow real-time alteration of routing
- The input to output delay is deterministic
- The configuration of the switch routing is under microprocessor control through an AXI-Lite interface
- Supports UltraScale devices
The IQ switch is targeted at wireless systems and uses an architecture that is scalable for use in baseband units, radio units or C-RAN aggregators. A simplified application is shown in Figure 1.
The IQ switch will be capable of routing any ingress timeslot signal to any egress port timeslot. An ingress timeslot signal can also be routed to multiple egress ports (multicast / broadcast). To achieve this the switching fabric is implemented as a 2D array of BRAM which are configured as dual port memory. The ingress data frame is duplicated in each BRAM in a row so every egress port has access to any IQ sample in a frame. An additional BRAM is used to provide a map so data from any timeslot in a frame can be routed to any timeslot on any egress port. Additional blocks provide de-skew and timing synchronization.
The resource utilization for selected configurations is shown below:
|16 Ports (8x8)
|32 Ports (16x16)||88||4000|
The IQ switch will be delivered as a package available on the IQ switch lounge. The package contains:
- The IQ Switch configured as 8x8 ports.
- Example design and scripts to implement the design in Vivado
- Test bench and simulation scripts
The IQ switch has been verified using the UVM methodology.