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  3. Display Stream Compression (VESA DSC) 1.2b Decoder IP Core

Display Stream Compression (VESA DSC) 1.2b Decoder IP Core

  • Part Number: DSC1.2-DEC-FPGA-XLNX
  • Vendor: Rambus, Inc.
  • Partner Tier: Elite
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Product Description

The Rambus DSC v1.2b Decoder IP Core implements video stream decompression functionality compliant with the VESA Display Stream Compression (DSC) v1.2(b) standard.

The DSC algorithms enable visually lossless compression for high-definition applications in the broadcast video, pro A/V, automotive, medical, and consumer electronics industries. Applications include video, graphics and display processors, video transport, display monitors, televisions, and DSC standard compliance test and measurement equipment.

The VESA DSC compression standard is compatible with several transport standards including MIPI DSI 1.2, VESA Embedded DisplayPort 1.4a, DisplayPort 1.4a, and HDMI 2.1.

DSC technology enables high resolutions such as 4K (4096x2160), 5K (UHD+), and 8K (FUHD) at higher color depths. Please contact Rambus for further information.

Key Features and Benefits

  • VESA Display Stream Compression (DSC) 1.2a compliant
  • Supports all DSC 1.2a mandatory and optional encoding mechanisms
  • Backward compatible to DSC v1.1
  • Configurable maximum display resolution up to 8K (FUHD)
  • 8, 10, and 12 bits per video component
  • YCbCr and RGB video output format
  • 4:4:4, 4:2:2, and 4:2:0 native coding
  • Resilient to bitstream corruption
  • 3 pixels / clock internal processing architecture in 4:4:4
  • 6 pixels / clock internal processing architecture in 4:2:2 and 4:2:0
  • Parameterizable number of parallel slice decoder instances (1, 2, 4, 8) to adapt to the capability of the technology and target display resolutions used
  • Automatic run time configuration of the number of parallel slice decoder instances in use
  • AXI-Stream interfaces for easy integration in IP integrator
  • AXI-Lite interface for register access
  • PPS 128 bytes block decoding
  • Compliant solution for DisplayPort 1.4 or HDMI 2.1
  • Compatibility for slices per line requirements
  • Supports flexible usage models and design architecture (inline decoding or panel frame buffer decoding)

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Kintex-UP Family XCKU15P -2 Vivado 2020.2 Y 8702 17403 15 1 0 0 215
KINTEX-7 Family XC7K325T -2 Vivado 2020.2 Y 8837 17674 15 1 0 0 115
KINTEX-U Family XCKU040 -2 Vivado 2020.2 Y 8945 17889 15 1 0 0 140

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 1.11
Date Current Revision was Released Jan 21, 2021
Release Date of First Version Jan 21, 2021

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 25
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Source Code, Netlist
Source Code Format(s) Verilog
High-Level Model Included? Y
Model Formats C
Integration Testbench Provided Y
Integration Test Bench Format(s) OVM System Verilog, Verilog
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? XDC
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? N
Driver OS Support Windows, Linux, OSX

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Other Optimization Techniques
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis / 2016; Vivado Synthesis / 2017; Vivado Synthesis / 2018; Vivado Synthesis / 2019; Vivado Synthesis / 2020; Vivado Synthesis / 2021
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite, AXI4-Stream
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor Questa

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Xilinx KC705, VCU108, VCU118, ZCU102
Industry Standard Compliance Testing Passed N/A
Are Test Results Available? N