TSN Endpoint IP

Product Description

Push your network performance to the absolute maximum while staying compliant to open standards and preparing your system for certification.

With modern networked systems, message transmission gets increasingly more difficult when more devices are connected, and missed messages mean that mission-critical responses to incoming threats aren't triggered in time.

DornerWorks TSN Endpoint IP is a certifiable packaged IP block that provides deterministic Ethernet through TSN to any AMD UltraScale+ design. DornerWorks TSN Endpoint IP makes it simple to add a new or legacy system onto a TSN network without adding a lot of software overhead.

The DornerWorks TSN Endpoint IP consists of a 1G Ethernet MAC, PTP core, time aware shaping core, and Credit base shaping core. This FPGA based TSN solution provides a certifiable design that can scale efficiently with evolving standards. The time aware shaping core in logic allows for scheduling as refined as 8ns. The PTP core includes packet transmission and calculations in logic so no additional software is needed. The TSN endpoint IP allows for up to 8 Traffic Queues, or Quality of Service (QoS).

Schedule a meeting to learn how the DornerWorks TSN Endpoint IP can enable your system with a certifiable, hardware based, TSN solution.


Key Features and Benefits

  • Allows selection of any of the QoS levels to be pre-emptible or express traffic
  • Time-aware shaper - IEEE 802-1Qbv
  • gPTP - IEEE 802.1AS slave and master
  • Certifiable
  • 8 QoS - IEEE 802.1Q-2018
  • Credit-based shaping - IEEE 802.1 Qav

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -2 Vivado ML 2021.2 Y 26171 23234 17 24 0 0 125

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 1.0
Date Current Revision was Released Jul 13, 2023
Release Date of First Version Jul 13, 2023

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 0
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Source Code, Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? XDC
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? Y
Driver OS Support Petalinux

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis
Static Timing Analysis Performed? N
AXI Interfaces AXI4-Stream
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected None
Timing Verification Performed? Y
Timing Verification Report Available N
Simulators Supported Xilinx lSim / 2021.2

Hardware Validation

Validated on FPGA N
Industry Standard Compliance Testing Passed N
Are Test Results Available? N