Product Description
HSR-PRP Switch is an IP Core for the implementation of High-availability Seamless Redundancy and Parallel Redundancy Protocols (HSR and PRP, IEC 62439-3-Clause 5 and 4 respectively). These are protocols for Reliable Ethernet communications.
HSR-PRP Switch is a full hardware solution that can be implemented on low-cost FPGA and MPSoC systems. Thus, IP is a flexible solution that can be connected to HSR rings, PRP LANs or will work as network bridges. It includes the most sophisticated features related to IEEE 1588v2, like Power-Utility profile and the special modes HSR-HSR and HSR-PRP needed to implement Quadboxes or to merge PRP networks with HSR ones.
In addition to PRP and HSR redundancy, HSR-PRP Switch implements IEEE 1588 clock synchronization clock via the IEC 61850-9-3 Precision Time Protocol.
Key Features and Benefits
- HSR and PRP in the same IP
- No software stack required: All-in-hardware solution
- Nanosecond range forwarding time for HSR modes
- No external RAM memory required
- CPU-less version: Implementable on low-cost FPGAs
- Redundant IEEE 1588v2 and P2P operation supported by hardware
- SMARToem and SMARTzynq Development Boards available
- 10/100/1000Base-TX and FX support
- Supervsion Frames Managed by hardware
- VLAN priority support
- Reserved queues for designated protocols
- Reference Designs for AMD/Avnet boards
- HSR-HSR, HSR-PRP supported modes for seamless PRP-HSR networks merging and Quadbox operation
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-UP-MPSoC Family | XCZU3CG | -1 | Vivado 2020.2 | Y | 5102 | 13622 | 32 | 0 | 0 | 0 | 125 |
| KINTEX-7 Family | XC7K30T | -1 | Vivado 2020.1 | Y | 5056 | 13522 | 31 | 0 | 0 | 0 | 125 |
| Zynq-7000 Family | XC7Z030 | -1 | Vivado 2020.2 | Y | 4968 | 13418 | 31 | 0 | 0 | 0 | 125 |
IP Quality Metrics
General Information
| This Data was Current On | Feb 12, 2024 |
| Current IP Revision Number | 22.02 |
| Date Current Revision was Released | Mar 01, 2023 |
| Release Date of First Version | Aug 01, 2012 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 25 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Bitstream, Netlist, Source Code |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Model Formats | Matlab |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Zynq-7000 |
| Software Drivers Provided? | Y |
| Driver OS Support | embedded Linux |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference, Instantiation |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Xilinx XST |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4 |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Executable and documented plan |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators Supported | Xilinx lSim; Mentor ModelSIM |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | SMARTzynq Brick |
| Industry Standard Compliance Testing Passed | Y |
| Specific Compliance Test | ZHAW Interoperability test |
| Test Date | Jun 22, 2020 |
| Are Test Results Available? | N |