DVB-RCS2 Turbo Decoder and Encoder

  • Part Number: CREONIC_TURBO_DVB_RCS2
  • Vendor: Creonic GmbH
  • Certified Alliance Member

Product Description

DVB-RCS2 (Digital Video Broadcast - Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digital data transmission via satellites. It uses a new 16-state double-binary turbo decoder that significantly outperforms its dated 8-state counterpart of DVB-RCS. DVB-RCS2 is the first standard to adopt these highest performance turbo codes. New modulation schemes (8-PSK and 16-QAM) help to increase spectral efficiency even further. The outstanding error correction performance of the DVB-RCS2 turbo decoder makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.

Applications
  • Satellite communication (Interactive Services, Professional Services, TDMA)
  • Applications with highest demands on forward error correction
  • Applications with the need for a wide range of code rates and block lengths
  • Your Benefits
  • Gains up to 4 dB compared to convolutional codes.
  • Design-time configuration of throughput for optimal resource utilization.
  • Low-power and low-complexity design.
  • Burst-to-burst on-the-fly configuration.
  • High block length and code rate granularity.
  • Configurable amount of turbo decoder iterations.


    Key Features and Benefits

    • Compliant with ETSI 301 545-2 V1.1.1 (2012-01) (DVB-RCS2)
    • Support for all turbo code block lengths and code rates as defined by the standard
    • Support for all modulation schemes (QPSK, 8-PSK, 16-QAM)
  • Device Implementation Matrix

    Device utilization metrics for example implementations of this core. Contact provider for more information.

    Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
    Zynq-UP-MPSoC Family XCZU15EG -2 Vivado 2019.1 0 9021 0 0 0 0 390

    IP Quality Metrics

    General Information

    This Data was Current On Oct 18, 2019
    Current IP Revision Number 3.0.3
    Date Current Revision was Released Jul 12, 2019
    Release Date of First Version Nov 02, 2012

    Production Use by Xilinx Customers

    Number of Successful Xilinx Customer Production Projects 5
    Can References be Made Available? N

    Deliverables

    IP Formats Available for Purchase Netlist, Source Code
    Source Code Format(s) VHDL
    High-Level Model Included? Y
    Model Formats C, C++, Matlab
    Integration Testbench Provided Y
    Integration Test Bench Format(s) VHDL
    Code Coverage Report Provided? Y
    Functional Coverage Report Provided? Y
    UCFs Provided? N
    Commercial Evaluation Board Available? N
    Software Drivers Provided? N

    Implementation

    Code Optimized for Xilinx? Y
    Standard FPGA Optimization Techniques Instantiation
    Custom FPGA Optimization Techniques None
    Synthesis Software Tools Supported/Version Xilinx XST
    Static Timing Analysis Performed? Y
    AXI Interfaces AXI4-Stream
    IP-XACT Metadata Included? N

    Verification

    Is a Document Verification Plan Available? Yes, document only plan
    Test Methodology Both
    Assertions N
    Coverage Metrics Collected Code, Functional
    Timing Verification Performed? N
    Timing Verification Report Available N
    Simulators Supported Other / Aldec RivieraPRO

    Hardware Validation

    Validated on FPGA N
    Industry Standard Compliance Testing Passed N
    Are Test Results Available? N