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  3. CoaXPress Multi-Link Multi-Stream Device IP

CoaXPress Multi-Link Multi-Stream Device IP

  • Part Number: CXP_MultiLink_MultiChannel_Device
  • Vendor: EASii IC
  • Partner Tier: Elite Certified
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Product Description

The CoaXPress Device IP Core enables the transmission of video streams of multiple cameras on single or multiple coaxial cables, at total transfer rate up to 100 Gbps. The CoaXPress Device IP Core is compliant with JIAA CXP-001-2019 CoaXPress 2.0 and JIAA CXP-001-2015 CoaXPress 1.1.1 standards.

Key Features and Benefits

  • Support all GenICam compliant image formats: rectangular and arbitrary shaped, area and line scan, single and multi tap, multiple regions of interest, all standard pixel formats
  • Up to 4 slave AXI4-stream interfaces for video streams
  • AMD 7 series Ultrascale and UltraScale+ compatible, IP-XACT support
  • AXI4-lite slave processor interface for application specific control between host and cameras
  • Multiple video-streams, up to 256 independent stream IDs
  • Trigger in/out interface with uplink latency of 3.4μs or 1.7µs
  • Selectable downlink connection rates from 1.25 Gbps to 12.5 Gbps, up to 8 coaxial connections per Device IP

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-U Family XCKU040 -2 Vivado 2020.1 Y 0 8300 11 1 0 1 200

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 2.0 R32
Date Current Revision was Released Nov 24, 2022
Release Date of First Version Feb 11, 2015

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 21
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist, Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? XDC
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? Y
Driver OS Support Bare Metal

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference, Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis; Other / Vivado
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite, AXI4-Stream
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Both
Assertions Y
Coverage Metrics Collected Code, Functional, Assertion
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Mentor Questa

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used KC705; AC701; ZC706; KCU105; ZCU102; ZCU106 + custom boards
Industry Standard Compliance Testing Passed Y
Specific Compliance Test CoaXPress Plugfest
Test Date Apr 18, 2023
Are Test Results Available? Y