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  3. SHA-3: SHA-3 Secure Hash Function Core

SHA-3: SHA-3 Secure Hash Function Core

  • Part Number: SHA-3
  • Vendor: CAST, Inc.
  • Partner Tier: Elite Certified
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Product Description

The SHA-3 IP core is a high-throughput, area-efficient hardware implementation of the SHA-3/Kaccak cryptographic hashing functions, compliant to NISTS’s FIPS 180-4 and FIPS 202 standards. The core can implement all four fixed-length hash functions (i.e. the SHA3-224, SHA3-256, SHA3-384, and SHA3-512) and both extendable output functions (i.e. SHAKE-128 and SHAKE-256) provisioned by the standards. The function can be dynamically selected at run-time. It’s throughput can optionally be optimized by using input message buffering, which allows it to receive new input while still processing the previous message. Also, the number of hashing rounds per clock is configurable at synthesis time, allowing users to constrain performance to save silicon resources when desired. The SHA-3 IP core can ensure data integrity and/or user authentication in a range of applications including IPsec and TLS/SSL protocol engines, encrypted data storage, secure processing systems, e-commerce, and financial transaction systems.

Key Features and Benefits

  • Supported Standards: FIPS 202/SHA-3 - Permutation-Based Hash and Extendable-Output functions & FIPS 180-4/Secure Hash Functions (limited to SHA-3 use)
  • Configuration Options: Bit-width of input and output data buses, number of input buffers, and number of permutations per cycle
  • Functionality: SHA-3 Hash accelerator, with run-time programmable hashing function
  • Throughput: Upto 16Gbps per core instance on Kintex Ultrascale+ (lowest speed grade)
  • FPGA Resources: From 4,800 LUTs to 20,000 LUTs depending on configuration

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Kintex-UP Family XCKU11P -1 Vivado ML 2021.2 0 4808 0 0 0 0 375
KINTEX-U Family XCKU085 -1 Vivado ML 2021.2 N 0 4816 0 0 0 0 275
Spartan-7 Family XC7S75 -1 Vivado ML 2022.1 0 4767 0 0 0 0 150
ARTIX-7 Family XC7A200T -1 Vivado ML 2022.1 0 4772 0 0 0 0 150

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 2.01
Date Current Revision was Released Dec 01, 2022
Release Date of First Version Feb 02, 2015

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 12
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) Verilog
High-Level Model Included? Y
Model Formats C
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? Y
Functional Coverage Report Provided? N
UCFs Provided? UCF & SDF
Commercial Evaluation Board Available? N
FPGA Used on Board N/A
Software Drivers Provided? N/A
Driver OS Support Not required

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST; Mentor Precision; Synplicity Synplify; Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Stream
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Synopsys VCS; Cadence NC-Sim; Mentor ModelSIM; Mentor Questa; Cadence IUS

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used KC705
Industry Standard Compliance Testing Passed N
Are Test Results Available? N