Product Description
The Nextera ST 2110 Video over IP core enables standards based media transport over IP for providing individual packetization of video, audio and metadata.
The ST 2110 Core Suite supports the following: ST 2110-10 - System Timing, ST 2110-20 - Uncompressed Video Stream, ST 2110-21 - Traffic Shaping, ST 2110-30 - Uncompressed Audio Stream, ST 2110-40 - Ancillary Data (Metadata), NMOS IS-04 - Discovery and Registration, NMOS IS-05 - Connection Management, NMOS IS-07 Event & Tally, NMOS IS-08 Audio Mapping, NMOS IS-09 System Parameters.
We also offer a field proven ST 2059 companion core that is designed to work seamlessly along side the ST 2110 core to offer a complete ecosystem for professional media over IP.
Key Features and Benefits
- Fully Integrated ST 2059 Core (Optional)
- NMOS Software Core, including IS-04, 05, and 08
- Optimized ST 2110 Hardware Core
- HD and UHD Video Support
- 2022-7 Failsafe Redundancy
- Support for Uncompressed or Compressed video
- IP Framer and Filter
- Delivered with Complete Reference Design
- Resolution and Network Speed Independent - Supports 1G, 10G, 25G, 100G
- Optional 2022-8 Add-in Core
- IPMX Support for JPEG-XS and Async Sources
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| KINTEX-U Family | XCKU040 | -2 | Vivado ML 2022.2 | Y | 100 | 1000 | 100 | 0 | 1 | 0 | 300 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | 2.1 |
| Date Current Revision was Released | Jan 16, 2018 |
| Release Date of First Version | Jan 16, 2018 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 20 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Netlist, Source Code |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Code Coverage Report Provided? | Y |
| Functional Coverage Report Provided? | Y |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Kintex UltraScale |
| Software Drivers Provided? | Y |
| Driver OS Support | Linux |
Implementation
| Code Optimized for Xilinx? | N |
| Standard FPGA Optimization Techniques | UltraFast Design Methodology |
| Synthesis Software Tools Supported/Version | Vivado Synthesis |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Lite, AXI4-Stream |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Both |
| Assertions | Y |
| Coverage Metrics Collected | Assertion, Functional, Code |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Xilinx lSim |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | KCU-105 |
| Industry Standard Compliance Testing Passed | Y |
| Specific Compliance Test | JT-NM Tested Program |
| Test Date | Aug 20, 2019 |
| Are Test Results Available? | Y |