Power Solutions

Information and tools for conquering the key challenges of power consumption

To successfully address your power requirements, Xilinx provides a complete solution that encompasses power estimators and analyzers, power-driven implementation tool algorithms and a variety of power-related documentation. You will find within these pages practical information and pointers to material applicable to any stage in the FPGA development cycle.

XPower Estimator (XPE)

We offer product-specific spreadsheet-based power estimation tools, delivering significant improvements in accuracy and ease-of-use when compared with other power estimation tools.

XPE Spreadsheets

Important Note: The following spreadsheets contain macros. You must set "Macro Security" within Excel to either Medium or Low for the spreadsheets to function (Tool > Macro > Security...).

FPGA Device Family	Last Update
Virtex®-6 Virtex-5	19-Jan-2010
Virtex-4	Mar. 16, 2009
Spartan®-6 Spartan-3A/3AN/3A DSP	Dec. 08, 2009
Spartan-3E	Apr. 8, 2009
Spartan-3	April 8, 2009

• Whitepaper - 7 Steps for Worst Case Power Estimation (PDF)
• Xilinx Power Estimator User Guide (PDF)

XPower Analyzer

Delivered with ISE® Design Suite, Xpower Analyzer provides accurate power analysis after design implementation, highlighting areas in the design for potential power reduction.

• XPower Analyzer delivered with ISE Design Suite

Web Power Tools

Web-based power tools designed to get accurate power estimates for older architectures.

• Web Power Tool Quick Start Guide
• Virtex-II Pro
• Virtex-II
• Virtex/Virtex-E

Power Optimization

Xilinx provides a complete solution from software tools to IC technologies to help you to optimize the total power consumption of your design.

 

• ISE Design Goals and Strategies: With goal-based implementation, ISE Design Suite 11 offers a simple, one-step process to specify power optimization leading to an average of 12% lower dynamic power for the Spartan-3A family and 10% for Virtex-5 families

Additional information on design tools properties to perform a power-optimized implementation:

• Map properties
• Par properties
• Virtex-5 FPGA System Power Design Considerations This white paper contains low power techniques that could be applied to other Xilinx FPGA families.