Through silicon process selection, architectural innovation, and robust power estimation and optimization tools, Xilinx All Programmable devices continue to deliver unrivaled system-level power reduction with each successive generation of All Programmable logic families.
With UltraScale and UltraScale+ device families, a low-power semiconductor process coupled with significant static and dynamic power gating results in up to 40% overall device-level power savings at 20nm over Xilinx 7 series FPGAs and SoCs —already the lowest-power programmable logic device leader — and up to 60% savings at 16nm. In addition to process node benefits at 20nm and 16nm, designers can leverage key architectural enhancements such as hardware-based clock gating, hardened BRAM cascading, DSP block efficiencies, and optimized transceivers to lower overall power consumption.
Through device-level optimizations and systems integration, UltraScale devices deliver dramatic system-level power savings over previous implementations:
As the only 28nm FPGAs and SoCs fabricated on a high-performance, low-power process (28HPL), 7 series devices offer lower total power consumption and superior performance per watt compared to competing solutions. Architectural and block level innovations unique to Xilinx add to the power advantages at every level. In addition, to ensure a smooth production rollout of your system, 7 series FPGAs and SoCs provide:
Meeting system power, thermal, and reliability requirements starts with credible power estimation and optimization.
The Xilinx Power Estimator (XPE) provides accurate power estimation, helping designers avoid costly power supply and thermal management changes late in the design cycle. XPE is transparent about all sources of power consumption to ensure a complete picture of the total power budget.
Competing solutions claim “lower power” by not discussing some sources of power consumption. For instance, competitors promote transceiver power based only on the PMA power. Transceiver power is actually the sum of the PMA, PCS, and static power associated with transceiver usage.
The Vivado™ Design Suite offers powerful and accurate power analysis, including:
Vivado offers push button power optimization that reduces dynamic power by an average of 18% and up to 30% with virtually no impact to performance. Fine-grained clock gating technology is automatically applied to reduce switching activity. Other FPGA companies claim to offer similar power optimization, but analysis of these solutions shows either minimal power reduction (default mode) or a major impact to performance (full power optimization mode).
|Default Power Optimization||Reported Dynamic Power Savings||7.5%||2%|
|Reported Dynamic Power Savings||18%||12%|
Every 7 series device is tested to published max static power specs to ensure power consumption at or typically below expectations. Competing solutions have repeatedly raised static power specs near or after production, or simply failed to report maximum static power altogether, forcing designers to re-evaluate system demands.
|Low end||No Change||No Max Static Power|
|Mid Range||No Change||~ 50% Increase|
|High End||No Change||~ 10-30% Increase|
Xilinx 7 series FPGAs and SoCs support power binning of devices to provide lower static and total power. Well-defined yield and process distribution models ensure a reliable supply in volume production. Competitors have introduced power binned devices only after standard devices failed to meet the original static power specifications in production, leaving questions around the volume availability of these products.
|Device Offering||-1I/-2I||-1I/-2I||-2LE(0.9V)||-1LI/-2LI||"L" Devices|
|Static Power Reduction||30%||45%||55%||62% - 65%||30%|
|Planned||From Beginning||After Production|
|Availability||Volume Production||After Production|