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Power Efficiency

Unrivaled System-level Power Reduction

Through careful selection of silicon process and power-conscious architecture design, Xilinx devices deliver power efficiency across all product portfolios, including Spartan-6, 7 series, UltraScale™, and UltraScale+™ FPGAs, and SoCs. With each generation, Xilinx broadens its power reduction capabilities, ranging from process enhancements, architectural innovations, aggressive voltage scaling strategies, and advanced software optimization strategies. More detail on portfolio-specific capabilities, silicon process advantages, and benchmark comparisons are shown below. Power estimation, thermal models, full software support, and demonstration boards are publically available for all families.

UltraScale+ FPGAs

Based on a high performance, low-power semiconductor process (TSMC 16nm FinFET+), the UltraScale+ device families delivers up to 60% overall device-level power savings over 7 series FPGAs and SoCs. Architectural enhancements include:

  • Hardware-based clock gating
  • Hardened BRAM cascading
  • DSP block efficiencies
  • Power-optimized transceivers

Through architectural innovation and a dual-voltage operation of the primary core fabric, UltraScale+ families more than double the performance-per watt-capabilities of 7 series families by realizing power reductions while improving overall performance.

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Zynq UltraScale+ MPSoCs

In addition to all the power reducing capabilities of UltraScale+ FPGA logic, Zynq UltraScale+ MPSoCs utilize multiple power islands and domains within the processing system for coarse-grain and fine-grain dynamic power gating to continually adjust power consumption to performance demands, lowering overall device power.

UltraScale FPGAs

Based on a low-power 20nm semiconductor process coupled with significant static and power gating, UltraScale FPGA families deliver up to 40% overall device-level power savings compared to 7 series FPGAs. Architectural enhancements shared with UltraScale+ devices include

  • Hardware-based clock gating
  • Hardened BRAM cascading
  • DSP block efficiencies
  • Power-optimized transceivers
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7 Series FPGAs & Zynq-7000 All Programmable SoCs

As the only 28nm FPGAs and SoCs fabricated on a high-performance, low-power process (28HPL), 7 series devices offer up to 50% total power reduction over previous generation families and superior performance per watt compared to competing 28nm solutions. Architectural and block-level innovations include:

  • Partial reconfiguration for static power savings
  • Multi-mode I/O control
  • Intelligent clock gating
  • Power binning and voltage scaling

View competitive benchmark summaries as well as detailed benchmark process.

Optimized Power Delivery Solutions

Power management requirements are very diverse and often unique to a customer design. As a result, no single power management design can provide the optimal solution. Xilinx partners with the industry’s leading power management companies to provide guidance on the power supply requirements of Xilinx products. These companies include:

Below you will find a selection of reference designs developed together with some of our power management partners. Designs are grouped by product family, however many of these reference designs can be easily modified and applied to other product families. Please contact our partners for additional information and guidance in relation to any designs shown below.

Zynq UltraScale+ MPSoCs

Vendor Reference Design Target Device(s)
Texas Instruments 25-30W Remote Radio Head ZU9EG, ZU15EG

Kintex and Virtex UltraScale FPGAs

Zynq-7000 All Programmable SoCs

7 Series FPGAs

Vendor Reference Design Target Device(s)
Analog Devices Artix-7 ARTY Development Board A35T

Zynq UltraScale+ MPSoCs utilize multiple power islands and domains within the processing system for coarse-grain and fine-grain dynamic power gating to continually adjust power consumption to performance demands, lowering overall device power. The FPGA fabric is based on the UltraScale+ FPGA.

The Zynq UltraScale+ MPSoC is the industry's first heterogeneous multiprocessor SoC (MPSoC) that combines multiple user programmable processors, FPGA and advanced power management capabilities. The combination of ARM Class A Application Processors, class R processors coupled with programmable logic (PL) each of them running on its power domain allows designers to move tasks to the appropriate processor with a specific power/performance profile or to the PL logic to accelerate demanding tasks further reduce energy consumption.

Modern power efficient designs requires usage of complex system architectures with several hardware options to reduce power consumption as well as usage of a specialized CPU to handle all power management requests coming from multiple masters to power on, power off resources and handle power state transitions. The challenge is to provide an intelligent software framework that complies to industry standard(IEEEP2415) and is able to handle all requests coming from multiple CPUs running different operative systems. Xilinx has created the (Power Management Framework) to support a flexible power management control through the platform management unit (PMU).

Embedded vision,  Advanced Driver Assistance, Surveillance, portable medical, IoT industrial applications are ramping up their demand for high performance heterogeneous SoC but they have a tight power budget.  Some of them are battery operated and, battery life is a concern. Some others such as cloud and data center have demanding cooling and energy cost, without mentioning their need to reduce environmental cost. Reliability is also an important factor as increased temperature lead to a decreased battery life and increased stress on the overall system circuitry. All of these application benefit from a flexible power management solution.

Power scaling to trade off performance with power

Zynq UltraScale+ MPSoC allows users to optimize power consumption through an integrated Hardware and Software Power Management solution. Depending on the application, Users can choose across a wide spectrum of power modes spanning from all On consuming 2.6W to power off RTC ON consuming 3µW.

Zynq UltraScale+ MPSoC Power Management Hardware Architecture

The Zynq UltraScale+ MPSoC has four different power domains.

  • Low-power domain (LPD)
  • Full-power domain (FPD)
  • PL power domain (PLPD)
  • Battery power domain (BPD)

Each power domain can be individually isolated. The platform management unit (PMU) on the LPD facilitates the isolation of each of the power domains. The Dual voltage Programmable Logic allows to choose between two profiles; high performance or low power.

Zynq UltraScale+ MPSoC Power Management Software Architecture

Power Management complexity is abstracted by Xilinx’s Power Management Framework. It is an intelligent software framework that complies to industry standard(IEEEP2415) and is able to handle all requests coming from multiple CPUs running different operative systems. This Power Management Framework supports a flexible power management control through the platform management unit (PMU).

Key Features:

Designed for heterogeneous multiprocessing system

  • Power state management of all devices
  • Centralized power state information through PMU
  • Embedded Energy Management Interface APIs (IEEE P2415)

Support Linux OS power management

Direct control of power management features for 3º party OS

  • 24 APIs included in the XilPM library
  • Processor unit suspend and wake up
  • Management of slaves devices such as memories and peripherals

Tools

Xilinx provides best-in-class tools to estimate pre-implementation power consumption, optimize for lowest power at every design stage, and provide extensive analysis for user-guided optimization. Below are a variety of power-related and Xilinx industry-leading hardware and software-based tools for designers to get started today.