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Enabling Next Generation ADAS and AD Systems

Automotive grade Zynq UltraScale+ MPSoC Product Advantages

The Xilinx Automotive XA Zynq® UltraScale+™ MPSoC family is qualified according to AEC-Q100 test specifications with full ISO26262 ASIL-C level certification. The product integrates a feature-rich 64-bit quad-core ARM® Cortex™-A53 and dual-core ARM Cortex-R5 based processing system (PS) and Xilinx programmable logic (PL) UltraScale architecture in a single device. This scalable solution is ideally suited for various automotive customer platforms by delivering the right performance/watt while integrating critical functional safety and security features.

Value Features
Smarter, Optimized & Most Secure Solution
  • Innovative ARM® + FPGA architecture for differentiation, analytics & control
  • Extensive OS, middleware, stacks, accelerators, and IP ecosystem
  • Multiple levels of hardware and software security
Unmatched Integration, Performance, and Power
  • Integration delivering the de facto programmable platform
  • Up to 5X system level performance per watt over Zynq-7000 SoCs
  • Architected to deliver lowest system power
Proven Productivity
  • Most flexible & scalable platform for maximum reuse and best TTM
  • Industry leading design tools, C/C++, Open CL design abstractions
  • Largest portfolio of SW & HW design tools and reference designs

Processing System (PS)

Features All Devices
Application Processing Unit Quad-core ARM Cortex-A53 MPCore with CoreSight; NEON & Single/Double Precision Floating Point; 32KB/32KB L1 Cache, 1MB L2 Cache
Real-Time Processing Unit Dual-core ARM Cortex-R5 with CoreSight; Single/Double Precision Floating Point; 32KB/32KB L1 Cache, and TCM
Embedded and External
Memory256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4; LPDDR3; External Quad-SPI; NAND; eMMC
General Connectivity

214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock; WatchDog Timers; Triple Timer Counters

High-Speed Connectivity 4 PS-GTR; PCIe Gen1/2; Serial ATA 3.1; DisplayPort 1.2a; USB 3.0; SGMII
Graphic Processing Unit ARM Mali™-400 MP2; 64KB L2 Cache

Programmable Logic (PL)

  ZU2EG ZU3EG
ZU4EV ZU5EV
System Logic Cells (K) 103 154 192 256
Memory (Mb) 5.3 7.6 18.5 23.1
DSP Slices 240 360 728 1,248
Video Code Unit (VCU)     1 1
Maximum I/O Pins 252 252 252 252
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Note: Some restrictions may apply. Refer to UG585, Zynq-7000 SoC Technical Reference Manual and DS188, XA Zynq-7000 SoC Overview for details.

Documentation

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