Hero Slide Images

Trade Faster, Trade Smarter

New Alveo UL3524 for Ultra-Low Latency Trading

Contact Us

Purpose-Built for Ultra-Low Latency (ULL) Performance

Less than 3ns transceiver latency* for high performance, deterministic trade execution


Custom Algorithms and AI-Enabled Trading Strategies

Developers can integrate low latency AI models into trading system using traditional FPGA design as well as open-source PyTorch development flows



For a Breadth of Fintech

Hardware acceleration for algorithmic trading, pre-trade risk analysis, and market data delivery

Purpose Built for Ultra-Low Latency Trading

Fast Trade Execution

The Alveo™ UL3524 is powered by a new Virtex UltraScale+™ FPGA built for electronic trading. The device features a breakthrough transceiver architecture to achieve less than 3ns latency for world-class trade execution*, delivering 7X greater performance vs. previous FPGA technology**.

Custom Algorithms and AI-Enabled Trading Strategies

Hardware Adaptability

Featuring 64 ultra-low latency transceivers, 780K LUTs of FPGA fabric, and 1,680 DSP slices of compute, the Alveo UL3524 accelerator card is built to accelerate custom trading algorithms in hardware, where traders can tailor their design to evolving strategies and market conditions.

The Alveo UL3524 accelerator card is supported by the Vivado™ Design Suite for traditional FPGA flows. AMD is also providing developers with the open-sourced and community-supported FINN development framework, enabling low-latency AI models to be deployed into high-performance trading systems.

Hardware Adaptability


Competitive Advantage in Capital Markets

Proprietary trading firms, hedge funds, market makers, brokerages, and data vendors can deploy the Alveo™ UL3524 accelerator for ULL algorithmic trading, pre-trade risk management, market data delivery, and more. The convergence of hardware acceleration, FPGA flexibility, and low latency networking ensures high performance and determinism across a breadth of use cases.

ULL Algorithmic Trading

ULL Algorithmic Trading

From complex algorithmic trading to market-making services

Pre-Trade Risk Management

Pre-Trade Risk Management

Perform pre-trade risk assessment and regulatory compliance at ultra-low latency

Market Data Delivery

Market Data Delivery

Provide real-time market data reliably for brokerages and exchanges


 Review collateral and additional documentation at GitHub to learn more about Alveo UL3524 specifications. Visit the master answer record for up-to-date information on known issues.

Getting Started

The Alveo UL3524 accelerator is supported by traditional RTL development flows using Vivado Design Suite.  Reference designs to evaluate latency and performance, as well as test other features of the card are available at the GitHub Repository.

Special licensing is required to enable the target Virtex™ UltraScale+ device. Developers can request access to the Alveo UL3524 Lounge for licensing and access to additional technical documentation.

server ready

Flexible Deployment

The Alveo UL3524 accelerator card can be deployed in 1U, 2U, and 4U servers—flexible for diverse server rack and form factor requirements.

The 1U Hypertec Orion HF X410R-G6 high-frequency server is now available, featuring a custom cooling system for the Alveo UL3524 accelerator card. Contact us for more information.

Alveo UL3524 accelerator

Contact Us

Product Inquiry

The Alveo™ UL3524 is now in production and now shipping. Contact us for product questions, pricing, and lead times

Sign up for FinTech updates

Join our subscriber list for the latest updates regarding FPGA-based acceleration solutions for FinTech.

*Testing conducted by AMD Performance Labs as of 8/16/23 on the Alveo UL3524 accelerator card, using Vivado Design Suite 2023.1 and running on Vivado Lab (Hardware Manager) 2023.1. Based on the GTF Latency Benchmark Design configured to enable GTF transceivers in internal near-end loopback mode. GTF TX and RX clocks operate at same frequency of ~644MHz with a 180 degrees phase shift. GTF Latency Benchmark Design measures latency in hardware by latching value of a single free running counter. Latency is measured as the difference between when TX data is latched at the GTF transceiver and when TX data is latched at the GTF receiver prior to routing back into the FPGA fabric. Latency measurement does not include protocol overhead, protocol framing, programmable logic (PL) latency, TX PL interface setup time, RX PL interface clock-to-out, package flight time, and other sources of latency. Benchmark test was run 1,000 times with 250 frames per test. Cited measurement result is based on GTF transceiver “RAW Mode”, where PCS (physical medium attachment) of the transceiver passes data ‘as-is’ to FPGA fabric. Latency measurement is consistent across all test runs for this configuration. System manufacturers may vary configurations, yielding different results. ALV-10

**Based on simulation comparison between Virtex UltraScale+ GTY transceivers and ultra-low latency GTF transceivers.