High-Speed Transceiver Pin Multiplexing
- Part Number:
- EF-DI-HSTPM-WW
- EF-DI-HSTPM-RLL-WW
- EF-DI-HSTPM-VIV-RLL-WW
- Re-distributable Limited License (RLL) available for Value Added Resellers. See Ordering Page for further details
- License: Core License Agreement
Product Description
The High-Speed Transceiver Pin Multiplexing (HSTPM) IP core provides a low latency and cycle accurate solution for off chip connectivity over AMD Gigabit Transceiver (GT’s). For emulation and prototyping use cases, the AMD HSTPM IP core is an ideal solution to increase and extend IO count and connectivity between devices. This connectivity solution allows emulation and prototyping platforms to scale to meet demands for increasing performance and capacity.
Key Features and Benefits
- Pin mux ratio from 32 to 8192 bits
- Selectable number of lanes per quad from 1 to 16 (Depending on Quad topology)
- Adjustable Line Rate (in Gbps)
- 0.5 Gbps to 28 Gbps(GTY-3devices).
- Reference clock options depending on selected line rates.
- Selectable Transceiver Types
- GTYE3 andGTYE4 – all speed grades
- GTHE3 and GTHE4 – (-2 and above speed grades) -1 supported in upcoming releases
- Selectable GT Locations
- Overwritable locations with XDC constraints
- Master Lane selection, for clock alignment and recovery.
- DRP Common:
- Post Implementation line rate change.
- PCS/PMA Loopback for Link characterization and running example design.
Resource Utilization
| Rate | Mux Ratio |
Lanes | LUT | FF | BRAM | URAM | DSP |
|---|---|---|---|---|---|---|---|
| 26g |
1024 |
4 |
6383 |
12910 | 0 | 0 | 0 |